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...uating the intrinsics is the preferred solution, then I think we should also have the langref also specify that there’s no guarantee of correction codegen *solely* on the basis of int/fp type overloading for intrinsics. What do you think? Amara > On Mar 11, 2019, at 1:23 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > >> On Mar 11, 2019, at 3:30 PM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi GlobalISel interested parties, >> >> A recent bug report (https://bugs.ll...

Yea. I think AMD chains the node they're expanding into, but they don't chain it into an _existing_ chain. e.g. adding A->B to the DAG is ok. But adding A->B and next C->D with B->C is the problem. I appreciate the input On Thu, Jul 16, 2020 at 2:04 PM Matt Arsenault <arsenm2 at gmail.com> wrote: > > > > On Jul 16, 2020, at 17:00, Hendrik Greving <hgreving at google.com> wrote: > > > > > No, non-sideeffecting operations can be legalized as compiler-rt calls > > > > Right, but not as "regular" nodes with side-eff...

> On Feb 26, 2019, at 7:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > > >> On Feb 26, 2019, at 4:18 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: >> >> >> >>> On Feb 26, 2019, at 7:01 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >>> >>> I don’t get what you mean by “applyMapping to d...

> On Apr 29, 2015, at 2:33 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > >> On Apr 29, 2015, at 10:06 AM, Silviu Baranga <Silviu.Baranga at arm.com <mailto:Silviu.Baranga at arm.com>> wrote: >> >> Note that dividing by an integer constant should be a cheap operation >> compared to FP multiplication and c...

...at sapo.pt>; > Stephen Canon <scanon at apple.com>; David Majnemer <david.majnemer at gmail.com>; > John Regehr <regehr at cs.utah.edu>; Sanjoy Das <sanjoy at playingwithpointers. > com>; Friedman, Eli <efriedma at codeaurora.org>; Matt Arsenault < > arsenm2 at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com> > > *Subject:* Re: how to simplify FP ops with an undef operand? > > > > Correct - NaN is not undef in IR. But we don't have a NaN in this example. > We have its moral equivalent in LLVM - an uninitia...

On Sep 15, 2014, at 4:17 PM, Owen Anderson <resistor at mac.com> wrote: > I’d be fine with that proposal. I could even be convinced if we wanted to add a pair of NaN-propagating intrinsics as well, for targets and languages that want those semantics, even if I disagree with them. I do think that, if we are using the minnum/maxnum names, we should explicitly note that they are

...tah.edu <mailto:regehr at cs.utah.edu>>; Sanjoy > Das <sanjoy at playingwithpointers.com > <mailto:sanjoy at playingwithpointers.com>>; Friedman, Eli > <efriedma at codeaurora.org <mailto:efriedma at codeaurora.org>>; Matt > Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>>; > Kreitzer, David L <david.l.kreitzer at intel.com > <mailto:david.l.kreitzer at intel.com>> > > > *Subject:* Re: how to simplify FP ops with an undef operand? > > Correct - NaN is not undef in IR...

...ISel and then having to > bother about chains, glue etc) > > > > Regards, > > Björn > > > > *From:* llvm-dev <llvm-dev-bounces at lists.llvm.org> *On Behalf Of *Hendrik > Greving via llvm-dev > *Sent:* den 16 juli 2020 23:35 > *To:* Matt Arsenault <arsenm2 at gmail.com> > *Cc:* llvm-dev <llvm-dev at lists.llvm.org> > *Subject:* Re: [llvm-dev] Selection DAG chain question > > > > Yea. I think AMD chains the node they're expanding into, but they don't > chain it into an _existing_ chain. e.g. adding A->B to the...

...yIntrinsic 0xbedb200, 0xbedac18 [ORD=4] The builtin in DAG looks like: 0xbedb2a8: i32,ch = llvm 0xbedb158:1, 0xbedb200, 0xbedb158 [ORD=7] [ID=16] The only difference I'm seeing is the extra operand, which is a 'ch' from a load. On Tue, Feb 2, 2016 at 3:55 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Feb 2, 2016, at 12:43, Ryan Taylor <ryta1203 at gmail.com> wrote: > > > > Matt, > > > > This seems to generate llvm.my_intrinsic just fine in the DAG, so no > DAG errors; however, it won't match. For example, if I cal...

On 8 Aug 2013, at 18:34, Matt Arsenault <arsenm2 at gmail.com> wrote: > I have the auto upgrade for turning bitcasts into inttoptr/ptrtoint implemented, but it isn't necessary with the current rule that same sized pointer bitcasts are allowed. This would be always necessary if all cross address space bitcasts were disallowed. The ptrt...

Awesome! What will the requirements be for the target? Is it sufficient to just override getPointerTy and add appropriate data layout strings, or will more hooks be needed? On Thu, Jul 25, 2013 at 3:41 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Jul 25, 2013, at 12:33 , Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > > Looking through recent additions, it looks like the infrastructure > exists for targets to specify a per-address-space pointer size/type, but > th...

...: llvm-dev <llvm-dev at lists.llvm.org>; Nuno Lopes <nunoplopes at sapo.pt>; Stephen Canon <scanon at apple.com>; David Majnemer <david.majnemer at gmail.com>; John Regehr <regehr at cs.utah.edu>; Sanjoy Das <sanjoy at playingwithpointers.com>; Matt Arsenault <arsenm2 at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com> Subject: Re: how to simplify FP ops with an undef operand? I'm pretty sure that isn't what nnan is supposed to mean. If the result of nnan math were undefined in the sense of "undef", programs using nnan co...

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For e...

> On Aug 21, 2018, at 17:57, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Matt, > I'm sorry, actually it's fma not fmad. > > In the post-legalizer DAG combine for the given code it's producing fma not fmad. That doens't seem correct. > The contract is on the fadd. I’m not really sure what the rule is supposed to be for contract between the nodes.

...> > The builtin in DAG looks like: > > 0xbedb2a8: i32,ch = llvm 0xbedb158:1, 0xbedb200, 0xbedb158 [ORD=7] [ID=16] > > The only difference I'm seeing is the extra operand, which is a 'ch' from a load. > > On Tue, Feb 2, 2016 at 3:55 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Feb 2, 2016, at 12:43, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: > > > > Matt, > > > > This seems to generate llvm.my_intrinsic just fine in the DAG,...

On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote: > >> >> Perhaps you're instead trying to say that with certain address spaces "noalias" (and by inference, "restrict" at the language level) has...

...insic from C, the DAG node looks to be named the same in dotty file but it won't match... am I missing something? I've done it exactly the way it was done above. The DAG looks great but it won't match. Did I miss something? Thanks. On Tue, Feb 2, 2016 at 2:47 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 11:27, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Matt, > > Is this an example you are talking about: > > LoadedVect = DAG.getNode > <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#ab02868bea...

> On Jul 24, 2017, at 13:52, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 06/13/2017 12:46 PM, Arsenault, Matthew via llvm-dev wrote: >> Hi, >> >> I want to be able to access a custom analysis pass during call lowering, but there isn't a way to access this now and I'm not sure the least bad way to thread this information into

On 01/07/2015 12:17 PM, Pete Cooper wrote: > >> On Jan 7, 2015, at 12:05 PM, Matt Arsenault <arsenm2 at gmail.com >> <mailto:arsenm2 at gmail.com>> wrote: >> >> >>> On Jan 7, 2015, at 2:55 PM, Philip Reames <listmail at philipreames.com >>> <mailto:listmail at philipreames.com>> wrote: >>> >>> >>> On 01/07/2015 1...

On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote: > > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result...