search for: arrayidx3

...nounwind define void @add(i32* noalias nocapture %a, i32* noalias nocapture %b, i32* noalias nocapture %c) #0 { entry: br label %for.body for.body: ; preds = %entry, %for.body %arrayidx.phi = phi i32* [ %b, %entry ], [ %arrayidx.inc, %for.body ] %arrayidx3.phi = phi i32* [ %c, %entry ], [ %arrayidx3.inc, %for.body ] %arrayidx5.phi = phi i32* [ %a, %entry ], [ %arrayidx5.inc, %for.body ] %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %0 = load i32* %arrayidx.phi, align 4, !tbaa !0 %1 = load i32* %arrayidx3.phi, align...

...assert(A[SZ/2] == B[SZ/2]); }* On running -O1 followed by -reg2mem I get the following IR: *define dso_local i32 @main() local_unnamed_addr #0 {entry: %A = alloca [2048 x i32], align 16 %B = alloca [2048 x i32], align 16 %"reg2mem alloca point" = bitcast i32 0 to i32 %arrayidx3 = getelementptr inbounds [2048 x i32], [2048 x i32]* %A, i64 0, i64 1024 %0 = load i32, i32* %arrayidx3, align 16 %arrayidx4 = getelementptr inbounds [2048 x i32], [2048 x i32]* %B, i64 0, i64 1024 %1 = load i32, i32* %arrayidx4, align 16 %cmp5 = icmp eq i32 %0, %1 %conv = zext i1 %cmp5 to i32...

Sent from my iPhone... On Jun 25, 2013, at 8:14 AM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> >> >> >> On Jun 24, 2013, at 4:24 PM, Hal Finkel < hfinkel at anl.gov > wrote: >> >> >> >> >> Indvars should ideally preserve NSW flags whenever possible. However, >> we don't want to

----- Original Message ----- > > > > On Jun 24, 2013, at 4:24 PM, Hal Finkel < hfinkel at anl.gov > wrote: > > > > > Indvars should ideally preserve NSW flags whenever possible. However, > we don't want to rely on SCEV to preserve them. SCEV expressions are > implicitly reassociated and uniqued in a flow-insensitive universe > independent of the

...; preds = %if.end br label %for.body for.body: ; preds = %for.body.preheader, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] %sum.011 = phi i32 [ %add, %for.body ], [ undef, %for.body.preheader ] %arrayidx3 = getelementptr inbounds i32, i32* %fooPtr, i64 %indvars.iv %1 = trunc i64 %indvars.iv to i32 store i32 %1, i32* %arrayidx3, align 4, !tbaa !7 %2 = load i32, i32* %arrayidx, align 4, !tbaa !7 %add = add nsw i32 %2, %sum.011 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %lftr.wideiv...

...; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %0 = shl nsw i64 %indvars.iv, 1 %arrayidx = getelementptr inbounds i32* %b, i64 %0 %1 = load i32* %arrayidx, align 4, !tbaa !1 %add = add nsw i32 %1, %I %arrayidx3 = getelementptr inbounds i32* %a, i64 %0 store i32 %add, i32* %arrayidx3, align 4, !tbaa !1 %2 = or i64 %0, 1 %arrayidx7 = getelementptr inbounds i32* %b, i64 %2 %3 = load i32* %arrayidx7, align 4, !tbaa !1 %add8 = add nsw i32 %3, %I %arrayidx12 = getelementptr inbounds i32* %a, i64 %2...

...pace(1)* %input, i32 %call %0 = load i32 addrspace(1)* %arrayidx, align 4, !tbaa !1 %call1 = tail call i32 @get_local_id(i32 0) #2 %arrayidx2 = getelementptr inbounds i32 addrspace(2)* %mask, i32 %call1 %1 = load i32 addrspace(2)* %arrayidx2, align 4, !tbaa !1 %add = add nsw i32 %1, %0 %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %output, i32 %call store i32 %add, i32 addrspace(1)* %arrayidx3, align 4, !tbaa !1 ret void } ; Metadata and other declarations omitted The IR for X86_64 now is: /// test.x86_64.ll /// target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-...

...%arrayidx1 = getelementptr inbounds [3 x <2 x i32>]* %sPrivateStorage, i64 0, i64 0 store <2 x i32> %0, <2 x i32>* %arrayidx1, align 8, !tbaa !9 %arrayidx2 = getelementptr inbounds <2 x i32>* %src, i64 1 %1 = load <2 x i32>* %arrayidx2, align 8, !tbaa !9 %arrayidx3 = getelementptr inbounds [3 x <2 x i32>]* %sPrivateStorage, i64 0, i64 1 store <2 x i32> %1, <2 x i32>* %arrayidx3, align 8, !tbaa !9 %arrayidx4 = getelementptr inbounds <2 x i32>* %src, i64 2 %2 = load <2 x i32>* %arrayidx4, align 8, !tbaa !9 %arrayidx5 =...

...float> addrspace(1)* noalias nocapture %out, <2 x float> addrspace(3)* nocapture %data0) #2 { entry: %0 = tail call <4 x i32> @__amdil_get_local_id_int() #2 %1 = extractelement <4 x i32> %0, i32 0 %arrayidx = getelementptr <2 x float> addrspace(3)* %data0, i32 %1 %arrayidx3 = getelementptr <2 x float> addrspace(1)* %in, i32 %1 %tmp4 = load <2 x float> addrspace(1)* %arrayidx3, align 8 store <2 x float> %tmp4, <2 x float> addrspace(3)* %arrayidx, align 8 tail call void @__amdil_barrier_local() #0 %cmp = icmp ult i32 %1, 5 br i1 %cmp, l...

Hello, I am performing alias analysis toward the following simple code: struct MyStruct { int * f1; int * f2; }; void NOALIAS(void* p, void* q){ } int main() { struct MyStruct s[2]; int a,b; s[0].f1 = &a; s[1].f1 = &b; NOALIAS(s[a].f1, s[b].f2); return 0; } When I use the following command to generate .bc code and conduct alias analysis: clang -c -emit-llvm t.c -O2 opt -basicaa

> -----Original Message----- > From: Michele Scandale [mailto:michele.scandale at gmail.com] > Sent: Saturday, August 10, 2013 6:29 AM > To: Micah Villmow > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Address space extension > > On 08/10/2013 02:47 PM, Micah Villmow wrote: > > Michele, > > The information you are trying to gather is fundamentally

On 07/04/2013 01:39 PM, Stéphane Letz wrote: > Hi, > > Our DSL can generate C or directly generate LLVM IR. With LLVM 3.3, we can vectorize the C produced code using clang with -O3, or clang with -O1 then opt -O3 -vectorize-loops. But the same program generating LLVM IR version cannot be vectorized with opt -O3 -vectorize-loops. So our guess is that our generated LLVM IR lacks some

Hi Pankaj, your best bet is to send the entire bitcode before and after instcombine runs. Ciao, Duncan.

Hi, Our DSL can generate C or directly generate LLVM IR. With LLVM 3.3, we can vectorize the C produced code using clang with -O3, or clang with -O1 then opt -O3 -vectorize-loops. But the same program generating LLVM IR version cannot be vectorized with opt -O3 -vectorize-loops. So our guess is that our generated LLVM IR lacks some informations that are needed by the vectorization passes to

With reference to the previous query, I think, i miscalculated the offset, just recalculating. 1. without instruction combining coupling member variable, is at:   %struct._FRAME_DATA* %2, i32 0, i32 5   where "%2" is defined as:   %arrayidx3 = getelementptr inbounds i16* %Data, i32 1024, !dbg !446   %2 = bitcast i16* %arrayidx3 to %struct._FRAME_DATA*, !dbg !446 i.e. at 5 offset in FRAME_DATA i.e. the 6th element, i.e. coupling member variable. i16, i16, i16, [6 x i16], [5 x i16], i16, i16, [3 x i16], [5x i16], [2 x i16], [5 x i32],...

...for.body: ; preds = %for.body.preheader, %for.body * %indvars.iv = phi i64 [ 10, %for.body.preheader ], [ %indvars.iv.next, %for.body ]* %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv %2 = load i32, i32* %arrayidx, align 4, !tbaa !1 %arrayidx3 = getelementptr inbounds i32, i32* %y, i64 %indvars.iv %3 = load i32, i32* %arrayidx3, align 4, !tbaa !1 %div = sdiv i32 %2, %3 %arrayidx5 = getelementptr inbounds i32, i32* %z, i64 %indvars.iv store i32 %div, i32* %arrayidx5, align 4, !tbaa !1 * %indvars.iv.next = add nuw i64 %indvars.iv,...

Hi LLVM developers, We tried to find if there are some passes in LLVM do the opposite of the SROA(Scalar Replacement of Aggregates) pass, but did not find one. Do we have this kind of pass to bring back the structure type? Or this is done separately in any transformation passes? Thanks, Lin-Ya -------------- next part -------------- An HTML attachment was scrubbed... URL:

...; preds = %for.body, %entry > %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] > %0 = shl nsw i64 %indvars.iv, 1 > %arrayidx = getelementptr inbounds i32* %b, i64 %0 > %1 = load i32* %arrayidx, align 4, !tbaa !1 > %add = add nsw i32 %1, %I > %arrayidx3 = getelementptr inbounds i32* %a, i64 %0 > store i32 %add, i32* %arrayidx3, align 4, !tbaa !1 > %2 = or i64 %0, 1 > %arrayidx7 = getelementptr inbounds i32* %b, i64 %2 > %3 = load i32* %arrayidx7, align 4, !tbaa !1 > %add8 = add nsw i32 %3, %I > %arrayidx12 = getelemen...

...ng `s[b].f2` is again using an > object while it is indeterminate and undefined behavior.) > > *** IR Dump After Promote Memory to Register *** > > ; the following corresponds to loading `s[a].f1` > %3 = load i32, i32* %a, align 4, !tbaa !7 > %idxprom = sext i32 %3 to i64 > %arrayidx3 = getelementptr inbounds [2 x %struct.MyStruct], [2 x > %struct.MyStruct]* %s, i64 0, i64 %idxprom > %f14 = getelementptr inbounds %struct.MyStruct, %struct.MyStruct* > %arrayidx3, i32 0, i32 0 > %4 = load i32*, i32** %f14, align 16, !tbaa !2 > %5 = bitcast i32* %4 to i8* > > ;...

Hi All,   I have been having this issue, when I am enable Instruction Combining pass, for an application. I have read similar post ealier, http://old.nabble.com/Instruction-Combining-Pass-*Breaking*-Struct-Reads--td24253572.html With reference to the above case, my target data layout is defined as: DataLayout("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-a:32:32") Thus I don't see