search for: array_lengthof

Displaying 19 results from an estimated 19 matches for "array_lengthof".

2012 Jul 26
2
[LLVMdev] Why is this assertion here?
I'm trying to understand why this assertion is here. LegalizeAction getCondCodeAction(ISD::CondCode CC, EVT VT) const { assert((unsigned)CC < array_lengthof(CondCodeActions) && (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && "Table isn't big enough!"); LegalizeAction Action = (LegalizeAction) ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);...
2012 Jul 26
2
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
...o: > uint64_t CondCodeActions[ISD::SETCC_INVALID][2]; > > setCondCodeAction then becomes: > void setCondCodeAction(ISD::CondCode CC, MVT VT, > LegalizeAction Action) { > assert(VT < MVT::LAST_VALUETYPE && > (unsigned)CC < array_lengthof(CondCodeActions) && > "Table isn't big enough!"); > CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &= > ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2); > CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64_t)Action > <&...
2012 Jul 26
0
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
...the definition of CondCodeAction to: uint64_t CondCodeActions[ISD::SETCC_INVALID][2]; setCondCodeAction then becomes: void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { assert(VT < MVT::LAST_VALUETYPE && (unsigned)CC < array_lengthof(CondCodeActions) && "Table isn't big enough!"); CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &= ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2); CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64_t)Action << (VT.SimpleTy - 32...
2012 Jul 26
0
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
...tions[ISD::SETCC_INVALID][2]; > > > > setCondCodeAction then becomes: > > void setCondCodeAction(ISD::CondCode CC, MVT VT, > > LegalizeAction Action) { > > assert(VT < MVT::LAST_VALUETYPE && > > (unsigned)CC < array_lengthof(CondCodeActions) && > > "Table isn't big enough!"); > > CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &= > > ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2); > > CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64...
2009 Feb 07
1
[LLVMdev] Patch: More data types
...// First promote to a power-of-two size, then expand if necessary. return VT == VT.getRoundIntegerType() ? Expand : Promote; assert(0 && "Unsupported extended type!"); return Legal; } unsigned I = VT.getSimpleVT(); assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])) ; return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); } void setTypeAction(MVT VT, LegalizeAction Action) { unsigned I = VT.getSimpleVT(); assert(I<4*array_lengthof(ValueTypeActions)*size...
2010 Jul 17
2
[LLVMdev] v16i32/v16f32
I tried adding them in my backend however I run into the assertion assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 && ExtType < array_lengthof(LoadExtActions) && "Table isn't big enough!"); What does the assertion mean ? thanks for all help!! shrey On Wed, Jul 14, 2010 at 6:56 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, Jul 14, 2010 at 6:48 PM, shreyas krishnan <shreyas76...
2010 Jul 17
0
[LLVMdev] v16i32/v16f32
On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote: > I tried adding them in my backend however I run into the assertion > >  assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 && >           ExtType < array_lengthof(LoadExtActions) && >           "Table isn't big enough!"); > > What does the assertion mean ? That means you forgot to bump up LAST_VALUETYPE. -Eli
2011 Mar 07
1
[LLVMdev] DW_TAG_lexical_block structure in debug information
...ntext, dwarf::DW_TAG_lexical_block), Scope, ConstantInt::get(Type::getInt32Ty(VMContext), Line), ConstantInt::get(Type::getInt32Ty(VMContext), Col), File, ConstantInt::get(Type::getInt32Ty(VMContext), unique_id++) }; return DILexicalBlock(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } Is this an error in the documentation? Thanks in advance, Eli
2011 Nov 08
0
[LLVMdev] [cfe-dev] LLVM 3.0rc3 Testing Beginning
...icOutput(APValue( APFloat(APFloat::IEEEdouble, "3.2"), APFloat(APFloat::IEEEdouble, "5.7"))) Actual: "" Expected: "3.200000e+00+5.700000e+00i" /home/jay/llvm/clang-3.0rc3.src/unittests/AST/APValueTest.cpp:80: Failure Value of: GetDiagnosticOutput(APValue(V, array_lengthof(V))) Actual: "" Expected: "[3, 4, 5]" [ FAILED ] APValue.Diagnostics (1 ms) [----------] 1 test from APValue (16 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test case ran. (16 ms total) [ PASSED ] 0 tests. [ FAILED ] 1 test, liste...
2010 Jul 15
2
[LLVMdev] v16i32/v16f32
Hi I find types such as v16i32, v16f32 missing in my llvm version 2.7 So does the following page not list them http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html is that intentional for any reason or can I just add them ? thanks shrey
2010 Jul 15
0
[LLVMdev] v16i32/v16f32
On Wed, Jul 14, 2010 at 6:48 PM, shreyas krishnan <shreyas76 at gmail.com> wrote: > Hi >   I find  types such as v16i32, v16f32  missing in my llvm version 2.7 > > So does the following page not list them > http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html > > is that intentional for any reason or can I just add them  ? As far as I know, they're not there
2010 Jul 17
1
[LLVMdev] v16i32/v16f32
...wrote: > On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote: >> I tried adding them in my backend however I run into the assertion >> >>  assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 && >>           ExtType < array_lengthof(LoadExtActions) && >>           "Table isn't big enough!"); >> >> What does the assertion mean ? > > That means you forgot to bump up LAST_VALUETYPE. > > -Eli >
2013 Mar 14
0
[LLVMdev] initial putback for implementing mips16/nomips16 attributes - please review
...45b792 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -958,6 +958,14 @@ protected: RegClassForVT[VT.SimpleTy] = RC; } + /// clearRegisterClasses - remove all register classes + void clearRegisterClasses() { + for (unsigned i = 0 ; i<array_lengthof(RegClassForVT); i++) + RegClassForVT[i] = 0; + while (!AvailableRegClasses.empty()) + AvailableRegClasses.pop_back(); + } + /// findRepresentativeClass - Return the largest legal super-reg register class /// of the register class for the specified type and its associated "c...
2011 Nov 07
6
[LLVMdev] LLVM 3.0rc3 Testing Beginning
Good day, LLVMers! We are starting on our third (and hopefully last) round of testing for LLVM 3.0. Please visit: http://llvm.org/pre-releases/3.0/rc3/ for the sources. There are also binaries for Darwin up there, with more to come during the week. Please build this release candidate, test it out on your projects, and let us know if you find any regressions from the 2.9 release. Please keep
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya
2011 Nov 08
4
[LLVMdev] [cfe-dev] LLVM 3.0rc3 Testing Beginning
...t(APFloat::IEEEdouble, > "3.2"), APFloat(APFloat::IEEEdouble, "5.7"))) > Actual: "" > Expected: "3.200000e+00+5.700000e+00i" > /home/jay/llvm/clang-3.0rc3.src/unittests/AST/APValueTest.cpp:80: Failure > Value of: GetDiagnosticOutput(APValue(V, array_lengthof(V))) > Actual: "" > Expected: "[3, 4, 5]" > [ FAILED ] APValue.Diagnostics (1 ms) > [----------] 1 test from APValue (16 ms total) > > [----------] Global test environment tear-down > [==========] 1 test from 1 test case ran. (16 ms total) > [ PASSED...
2012 Oct 10
2
[LLVMdev] Solicit code review (change to CodeGen)
...} + + if (CC == X86::COND_E && + CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) { + SDValue Ops[] = { FalseOp, Cond.getOperand(0), N->getOperand(2), Cond }; + return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops, + array_lengthof(Ops)); + } + } + } + return SDValue(); } Index: test/CodeGen/X86/select_const.ll =================================================================== --- test/CodeGen/X86/select_const.ll (revision 0) +++ test/CodeGen/X86/select_const.ll (revision 0) @@ -0,0 +1,16 @@ +; RUN: llc < %...
2012 May 25
3
[LLVMdev] Predicate registers/condition codes question
On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop <spop at codeaurora.org> wrote: > On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> Sebastian, >> >> First, it might be useful to look at what is done in the PowerPC >> backend. PPC also has condition registers that are larger than the >> 1-bit conditional results, and it defines
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...micOrdering SuccessOrdering, AtomicOrdering FailureOrdering, + SynchronizationScope SynchScope) : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) { - InitAtomic(Ordering, SynchScope); + InitAtomic(SuccessOrdering, FailureOrdering, SynchScope); assert((DynOps || NumOps <= array_lengthof(Ops)) && "Too many ops for internal storage!"); InitOperands(DynOps ? DynOps : Ops, AllOps, NumOps); @@ -1151,6 +1167,16 @@ public: const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getVal() const { return getOperand(2); }...