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armv2
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
Hi,
For my research, I need to reshape the current ARM backend to support
armv2a. Zero-extend half word load (ldrh) is not supported by armv2a, so I
need to make the code generation to not generate ldrh instructions. I want
to replace all those instances with a 32-bit load (ldr) and then and the
result with 0xffff to mask out the upper bits.
These are the modifications that...