search for: armschedule

...ome digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen. --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote: > From: Carter Cheng <carter_cheng at yahoo.com> > Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc. > To: llvmdev at cs.uiuc.edu > Date: Monday, August 17, 2009, 2:56 PM > I apologize if this has been asked > before but which classes utilize the information in these > files? I am asking since I am trying to extend the MIPS > backend to 64bit among other t...

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things. Thanks in advance, Carter.

.... I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages. See /include/llvm/Target/TargetInstrItineraries.h for some information. The CortexA8Itineraries description in ARMScheduleV7.td is where I am using these new features to model the Cortex-A8. All of this is a work in progress... I suppose when I finish I will write up something describing the new Itinerary model and how to use it... David On Aug 18, 2009, at 1:11 AM, Carter Cheng wrote: > Actually after so...