search for: armloadstoreoptim

...t; Evan & llvmdev, > > I'm seeing a case where ARM Load/Store optimizer is breaking code. I have not had any luck trying to come up with a minimal example; it is breaking in our stage 2 LLVM build. > > But here's what I'm seeing in the debug output: > > # Before ARMLoadStoreOptimizer: > BB#21: derived from LLVM BB %cond.end > Live Ins: %LR %R0 %R1 %R7 %R10 %R11 > Predecessors according to CFG: BB#14 BB#18 > STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; mem:ST4[%first257](tbaa=!"int") > %R1<def> = ADDri %R1<ki...

...> I'm seeing a case where ARM Load/Store optimizer is breaking code. I > have not had any luck trying to come up with a minimal example; it is > breaking in our stage 2 LLVM build. > > > > But here's what I'm seeing in the debug output: > > > > # Before ARMLoadStoreOptimizer: > > BB#21: derived from LLVM BB %cond.end > > Live Ins: %LR %R0 %R1 %R7 %R10 %R11 > > Predecessors according to CFG: BB#14 BB#18 > > STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; > mem:ST4[%first257](tbaa=!"int") > > %R...

Evan & llvmdev, I'm seeing a case where ARM Load/Store optimizer is breaking code. I have not had any luck trying to come up with a minimal example; it is breaking in our stage 2 LLVM build. But here's what I'm seeing in the debug output: # Before ARMLoadStoreOptimizer: BB#21: derived from LLVM BB %cond.end Live Ins: %LR %R0 %R1 %R7 %R10 %R11 Predecessors according to CFG: BB#14 BB#18 STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; mem:ST4[%first257](tbaa=!"int") %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:...

Hello David, > I'm seeing a case where ARM Load/Store optimizer is breaking code. I have > not had any luck trying to come up with a minimal example; it is breaking in > our stage 2 LLVM build. Still, *any* testcase is better than no testcase :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Anton, I'm afraid I really can't produce a meaningful example. The bug is extremely sensitive to code placement, optimization. I had to do a terrible amount of drugdery to find it in the first place. Here's how I found the bug: 1) Stage 1: Compile LLVM with build/host x86, target ARM. 2) Stage 2: Cross-compile LLVM with host ARM, target ARM, using the stage 1 Clang/LLVM. 3) Use the

...could ask a few questions I have about working with the LLVM codebase. My thesis involves optimizing the way that LLVM deals with memory operations when targeting the ARM processor (specifically the ARM and Thumb-2 ISAs). Specifically, I'm writing a pass that runs just before the passes in the ARMLoadStoreOptimizer.cpp file. I've already devised an algorithm that I believe will work, and have it mostly implemented in LLVM, but I'm having trouble with some of the details. Specifically, I'm trying to rearrange the MachineInstrs within each MachineBasicBlock. I've noticed that there are seve...

...r_tag,llvm::MachineInstr,int,llvm::MachineInstr*,llvm::MachineInstr&>> = {<No data fields>}, <No data fields>}, NodePtr = 0x5a5a5a5a}) at STLExtras.h:154 #5 0x085c08c8 in LoadStoreMultipleOpti (this=0x29005ec0, MBB=@0x2904c400) at /home/emil/ll/llvm-2.1/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:683 #6 0x085c0a8e in runOnMachineFunction (this=0x29005ec0, Fn=@0x290282c0) at /home/emil/ll/llvm-2.1/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:744 #7 0x0853d4b8 in llvm::MachineFunctionPass::runOnFunction (this=0x29005ec0, F=@0x29007420) at MachineFunctionPass.h:41 #8 0x08b48a5d...

On Tue, Sep 18, 2007 at 06:41:38PM +1000, Emil Mikulic wrote: > The "make check" produced: > === Summary === > > # of expected passes 2209 > # of unexpected failures 41 > # of expected failures 5 > gmake[1]: *** [check-local] Error 1 > gmake[1]: Leaving directory `/home/emil/ll/objdir-llvm/test' > gmake: ***

...achineInstr*,llvm::MachineInstr&>> = {<No data fields>}, > <No data fields>}, NodePtr = 0x5a5a5a5a}) > at STLExtras.h:154 > #5 0x085c08c8 in LoadStoreMultipleOpti (this=0x29005ec0, > MBB=@0x2904c400) > at /home/emil/ll/llvm-2.1/lib/Target/ARM/ > ARMLoadStoreOptimizer.cpp:683 > #6 0x085c0a8e in runOnMachineFunction (this=0x29005ec0, > Fn=@0x290282c0) > at /home/emil/ll/llvm-2.1/lib/Target/ARM/ > ARMLoadStoreOptimizer.cpp:744 > #7 0x0853d4b8 in llvm::MachineFunctionPass::runOnFunction > (this=0x29005ec0, > F=@0x29007420) at...

On Nov 28, 2010, at 8:29 PM, Isaac Asay wrote: > > I am continuing to look over the code in the ARMLoadStoreOptimizer.cpp file, but I was wondering if you had a specific suggestion or a documentation resource that I could use to perform this instruction rearrangement in an LLVM idiomatic way. Using my algorithm, I already know where I can move MachineInstrs without effecting program correctness, but I don'...

Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD instruction. Ops.pop_back(); Ops.pop_back(); // Form the pair instruction. if (isLd) { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc))...

Hi Renato, Thanks for the response. While it is true that creating an IR optimization gives a better return due to it being applicable to any target ASM, there are also a lot of target specific optimizations that devs have felt are worthwhile enough to create, such as the ARMLoadStoreOptimizer.cpp file which contains ARM specific ASM optimizations. So I know that target specific optimizations are being created and tested, and since I've already gone and created the target specific optimization I'd like to be able to validate that it's working as expected in different test...

Hi Renato, > > I'm trying to add pseudo 64-bit load and store instructions for AArch64, which > > should have latencies set to "1" while being otherwise exactly the same as > > normal load and store instructions. > > Can I ask why would you need that? This is the only way I found to stop Machine Instruction Scheduler from reordering load and store

...is correct, just sub-optimal so is it appropriate to submit a bug report? - Is anyone already tackling this change or is there someone with more experience interested in collaborating? - Is this optimization better performed early during instruction selection or late using c++ (i.e. ARMLoadStoreOptimizer.cpp) - What is the potential to cause harm to other parts of the code gen, specifically for other arm targets. I'm working with armv6m, but armv7m offers base register updating in a single instruction. I don't want to break other useful optimizations. So far, I am reading t...

On 10 December 2012 03:00, Isaac Asay <iasay at calpoly.edu> wrote: > I've also tried using asm() C calls to force a > specific assembly pattern, but LLVM appears to treat the asm() call like a > single atomic block that does not have the optimizer run on its member > instructions. Hi Isaac, AFAIK, inline assembly is only exported at the end and it's generally kept

...ating a MachineFunctionPass, get all load and store instructions and add an instruction that writes the operands of Load/Store instructions to an address. How can I control the address of instrumentation ? I think getting all load and store instructions will be easy (I will do something similar to ARMLoadStoreOptimizer.cpp). However, I don't know how to control the instrumentation address. Can anybody give me pointer on this ? Or any other tips/recommendations are appreciated as well. Thank you very much for your help and time. Best Regards, MAW -------------- next part -------------- An HTML attachment...

My name is Isaac. I emailed this mailing list a couple years ago because I was working on an ARM specific target optimization for my thesis, and had questions about moving instructions and properly migrating kill flags. I have managed to get that working properly, and I now have a complete optimization that I wish to test. My question is simply this: Is there any established way to inject ARM

...imal so is it appropriate > to submit a bug report? > - Is anyone already tackling this change or is there someone with more > experience interested in collaborating? > - Is this optimization better performed early during instruction > selection or late using c++ (i.e. ARMLoadStoreOptimizer.cpp) > - What is the potential to cause harm to other parts of the code gen, > specifically for other arm targets. I'm working with armv6m, but armv7m > offers base register updating in a single instruction. I don't want to > break other useful optimizations. &gt...

On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,