search for: arminstrvfp

.... I'm doing this for ARM platform and the flag should be reachable from all these places in LLVM: - lib/Analysis/ValueTracking.cpp - lib/CodeGen/SelectionDAG/SelectionDAG.cpp - lib/IR/ConstantFold.cpp - lib/Target/ARM/ARMFastISel.cpp - lib/Target/ARM/ARMISelLowering.cpp - lib/Target/ARM/ARMInstrVFP.td (through predicates) - lib/Target/ARM/ARMRegisterInfo.td (through predicates) and in Clang: - lib/AST/ExprConstant.cpp Did I get it right and there is no such flag so far? Does what I'm suggesting sounds reasonable? Thanks, Sergey

...> done in LLVM using SelectionDAGs and the TableGen tool and it's > domain-specific language. > > Start by looking at llvm/lib/Target/ARM/ARMInstrInfo.td and seeing how > the basic instructions are matched. For armv7/armv7a, a new file will > want to be created similar to how ARMInstrVFP.td is sequestered. OK, I've got enough to go on with, and I'm getting ready right now to begin reading the dragon book, but one question bothers me regarding the present setup of llvm: the use of the present Makefile tools (dmake & gmake). I was rather surprised to find that a projec...

...it. Instruction selection is done in LLVM using SelectionDAGs and the TableGen tool and it's domain-specific language. Start by looking at llvm/lib/Target/ARM/ARMInstrInfo.td and seeing how the basic instructions are matched. For armv7/armv7a, a new file will want to be created similar to how ARMInstrVFP.td is sequestered. deep On Thu, May 21, 2009 at 2:40 PM, Chuck Robey <chuckr at telenix.org> wrote: > Christophe Avoinne wrote: >> Hi, >> >> - Cortex-A8 needs a specific instruction scheduler as dual issue forces >> you to interleave some instructions to allow to...

...> done in LLVM using SelectionDAGs and the TableGen tool and it's > domain-specific language. > > Start by looking at llvm/lib/Target/ARM/ARMInstrInfo.td and seeing how > the basic instructions are matched. For armv7/armv7a, a new file will > want to be created similar to how ARMInstrVFP.td is sequestered. > Just wanted to say, privately, I hugely appreciate this mail, I really want to thank you! I'm going to see what kind of trouble I have working my way through the Dragon book ... I know that, at school, it had a reputation of being able to drive students completely cra...

...all these places in LLVM: > > A - lib/Analysis/ValueTracking.cpp > A - lib/CodeGen/SelectionDAG/SelectionDAG.cpp > A - lib/IR/ConstantFold.cpp > A - lib/Target/ARM/ARMFastISel.cpp > A - lib/Target/ARM/ARMISelLowering.cpp > A - lib/Target/ARM/ARMInstrVFP.td (through predicates) > A - lib/Target/ARM/ARMRegisterInfo.td (through predicates) > > and in Clang: > > A - lib/AST/ExprConstant.cpp > > Did I get it right and there is no such flag so far?A Does what I'm > suggesting sounds reasonable? &g...

Christophe Avoinne wrote: > Hi, > > - Cortex-A8 needs a specific instruction scheduler as dual issue forces > you to interleave some instructions to allow to run two instructions in > the same cycle for the best performance (Cortex-A9 is out-of-order so > dual issue is not an issue (!) for performance). > - Cortex-A8/A9 have several useful new instructions : for instance,

Hi, - Cortex-A8 needs a specific instruction scheduler as dual issue forces you to interleave some instructions to allow to run two instructions in the same cycle for the best performance (Cortex-A9 is out-of-order so dual issue is not an issue (!) for performance). - Cortex-A8/A9 have several useful new instructions : for instance, bit operations like bitfield insertion/extraction or having

...gt; A - lib/Analysis/ValueTracking.cpp > >> A - lib/CodeGen/SelectionDAG/SelectionDAG.cpp > >> A - lib/IR/ConstantFold.cpp > >> A - lib/Target/ARM/ARMFastISel.cpp > >> A - lib/Target/ARM/ARMISelLowering.cpp > >> A - lib/Target/ARM/ARMInstrVFP.td (through predicates) > >> A - lib/Target/ARM/ARMRegisterInfo.td (through predicates) > >> > >> and in Clang: > >> > >> A - lib/AST/ExprConstant.cpp > >> > >> Did I get it right and there is no such flag so far?A D...