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2015 Dec 14
2
Tablegen definition question
Hi All, In ARMInstFormats.td predicate is defined this way: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),* *(ops (i32 14), (i32 zero_reg))> {...}* I use the same definition in my code. But I have another version of predicate which is exactly the same but it is a condition code plus a quantifier! (e....
2015 Dec 14
2
Tablegen definition question
...tened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32 zero_reg))> {...} > > On Mon, 14 Dec 2015 at 10:21 Sky Flyer via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi All, >> >> In ARMInstFormats.td predicate is defined this way: >> >> >> >> *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),* >> *(ops (i32 14), (i32 zero_reg))> {...}* >> >> >> I use the same definition in my code. But I have another version of >> predicate...
2015 Dec 14
2
Tablegen definition question
...rVT, (ops *i32imm, i32imm*, i32imm), >>> (ops (i32 14), (i32 zero_reg))> {...} >>> >>> On Mon, 14 Dec 2015 at 10:21 Sky Flyer via llvm-dev < >>> llvm-dev at lists.llvm.org> wrote: >>> >>>> Hi All, >>>> >>>> In ARMInstFormats.td predicate is defined this way: >>>> >>>> >>>> >>>> *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),* >>>> *(ops (i32 14), (i32 zero_reg))> {...}* >>>> >>>> >>>> I use the same definit...