search for: armgensubtargetinfo

...ok, but Clang can't see them. If I enable Clang to see them (by adding the include dir on the path), there will be nothing to stop people from including more than they should. The kind of information I want to expose are the enums that identify features, mainly VFP/NEON/Crypto etc. This is in ARMGenSubtargetInfo.inc under GET_SUBTARGETINFO_ENUM. One way I could think of, but it's controversial, is to generate two files: ARMGenSubtargetInfo.inc and ARMGenSubtargetInfoPublic.inc, the former in the current directory, the latter in a shared include path for all tools. That way, not only LLVM, but also Cl...

...to have to choose now and get it wrong. I realise that this might not have been the best course of action. Having said that, we can always go back. So, I'm open to suggestions. I could start with only a few per arch, and then add as we see fit. My guess is that only ARMGenRegisterInfo.inc and ARMGenSubtargetInfo.inc would be a good start, with possibly ARMGenCallingConv.inc and ARMGenInstrInfo.inc being the next ones to add for Clang's benefit. That would mean separating the calls to tablegen() between CMakeLists.txt and CMakeTblgen.txt, but that's ok. cheers, --renato

Thanks Bradley. I see that the features set in /ARM.td/ get written to the generated file /<build>/llvm/lib/Target/ARM/ARMGenSubtargetInfo.inc./ Here the ProcA9 features appear in /ARMFeatureKV/ table: /{ "a9", "Cortex-A9 ARM processors", { ARM::ProcA9 }, { *ARM::FeatureFP16* } }, /With your change, the features for ProcA9 in the above entry are empty.//This ARMFeatureKV table is then read in MC/MCSubtargetInf...

...), because this class initialized the Triple. i supposed that all the ARM machines need to initialize their own Triple info with ARMSubtarget(). however, to my frustrated, this doesnt seem true, and i still cannot find them anywhere in the source code. i looked at the table gen file lib/Target/ARM/ARMGenSubtargetInfo.inc, but dont see anything useful. i must missed something. any hint, please? thanks a lot, Jun -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130819/a0872cdc/attachment.html>

On 9 March 2015 at 17:40, Renato Golin <renato.golin at linaro.org> wrote: > The only way I can think of solving this is to change how tablegen() > handles the file name, with some "if(IS_ABSOLUTE)", but looking > further, the file name is used to more than just a filename, and gets > included in some variables names, etc. Also, I can't add another > option to

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

Hi Bradley, I was doing some performance analysis for ARMv7 (cortex-a9) and I noticed that one of my benchmarks degraded by 93%. I have tracked the regression down to the following commit by you: / //commit 7c1b77248baaeafec5d6433c3d1da9a2e2b69595// //Author: Bradley Smith <bradley.smith at arm.com>// //Date: Mon Nov 16 11:10:19 2015 +0000// // [ARM] Introduce subtarget features per

...new model, it's important to run table-gen with subtarget-emitter. You should be able to touch your .td, then grab the command via make TOOL_VERBOSE=1 This is the line from ARM: llvm-tblgen -I /s/fix/lib/Target/ARM -I /s/fix/include -I /s/fix/include -I /s/fix/lib/Target -gen-subtarget -o ARMGenSubtargetInfo.inc /s/fix/lib/Target/ARM/ARM.td -debug-only=subtarget-emitter It will list all instructions and print "No machine model for <subtarget>" You will also get an assert in the scheduler, unless you add the following flag to your mode: let CompleteModel = 0; That's perfect, tha...

.../null +++ b/lib/Target/ARM/.gitignore @@ -0,0 +1,13 @@ +ARMGenAsmMatcher.inc +ARMGenAsmWriter.inc +ARMGenCallingConv.inc +ARMGenCodeEmitter.inc +ARMGenDAGISel.inc +ARMGenEDInfo.inc +ARMGenFastISel.inc +ARMGenInstrInfo.inc +ARMGenMCCodeEmitter.inc +ARMGenMCPseudoLowering.inc +ARMGenRegisterInfo.inc +ARMGenSubtargetInfo.inc +ARMGenDisassemblerTables.inc diff --git a/lib/Target/CellSPU/.gitignore b/lib/Target/CellSPU/.gitignore new file mode 100644 index 0000000..6d3f2d2 --- /dev/null +++ b/lib/Target/CellSPU/.gitignore @@ -0,0 +1,7 @@ +SPUGenAsmWriter.inc +SPUGenCallingConv.inc +SPUGenCodeEmitter.inc +SPUGenDAGISe...