Displaying 4 results from an estimated 4 matches for "armgenregisterinfo".
2015 Mar 10
3
[LLVMdev] TargetParser - Always build all table-gen files?
...e because I didn't want to have
to choose now and get it wrong. I realise that this might not have
been the best course of action.
Having said that, we can always go back. So, I'm open to suggestions.
I could start with only a few per arch, and then add as we see fit. My
guess is that only ARMGenRegisterInfo.inc and ARMGenSubtargetInfo.inc
would be a good start, with possibly ARMGenCallingConv.inc and
ARMGenInstrInfo.inc being the next ones to add for Clang's benefit.
That would mean separating the calls to tablegen() between
CMakeLists.txt and CMakeTblgen.txt, but that's ok.
cheers,
--renato
2013 Feb 20
1
[LLVMdev] Question about accessing coprocesser register in prologue
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2015 Mar 10
2
[LLVMdev] TargetParser - Always build all table-gen files?
On 9 March 2015 at 17:40, Renato Golin <renato.golin at linaro.org> wrote:
> The only way I can think of solving this is to change how tablegen()
> handles the file name, with some "if(IS_ABSOLUTE)", but looking
> further, the file name is used to more than just a filename, and gets
> included in some variables names, etc. Also, I can't add another
> option to
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...000000..885bdf1
--- /dev/null
+++ b/lib/Target/ARM/.gitignore
@@ -0,0 +1,13 @@
+ARMGenAsmMatcher.inc
+ARMGenAsmWriter.inc
+ARMGenCallingConv.inc
+ARMGenCodeEmitter.inc
+ARMGenDAGISel.inc
+ARMGenEDInfo.inc
+ARMGenFastISel.inc
+ARMGenInstrInfo.inc
+ARMGenMCCodeEmitter.inc
+ARMGenMCPseudoLowering.inc
+ARMGenRegisterInfo.inc
+ARMGenSubtargetInfo.inc
+ARMGenDisassemblerTables.inc
diff --git a/lib/Target/CellSPU/.gitignore b/lib/Target/CellSPU/.gitignore
new file mode 100644
index 0000000..6d3f2d2
--- /dev/null
+++ b/lib/Target/CellSPU/.gitignore
@@ -0,0 +1,7 @@
+SPUGenAsmWriter.inc
+SPUGenCallingConv.inc
+SPUGenCode...