search for: armgendagisel

Hi, Today I downloaded LLVM 1.8 (until yesterday I used 1.7) and I tried to build it (Slackware 10.2 with default GCC 3.3.6). However, the build process fails each time it reaches lib/Target/XXX/XXXISelDAGToDAG.cpp for all backends (XXX=X86, ARM, ...), e.g. like: /.../llvm-build/lib/Target/ARM/ARMGenDAGISel.inc:145: error: syntax error before `{' token ... [lots of other errors generated by the previous one] /.../llvm-build/lib/Target/ARM/ARMGenDAGISel.inc:191: error: syntax error before `{' token ... [lots of other errors generated by the previous one] ... The NOINLINE-macro after e...

...ector implementation with tblgen assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function "ApplyTypeConstraints" gmake[3]: *** [/tmp/llvm/lib/Target/ARM/Debug/ARMGenDAGISel.inc.tmp] Abort trap (core dumped) gmake[3]: Leaving directory `/tmp/llvm/lib/Target/ARM' gmake[2]: *** [ARM/.makeall] Error 2 gmake[2]: Leaving directory `/tmp/llvm/lib/Target' gmake[1]: *** [Target/.makeall] Error 2 gmake[1]: Leaving directory `/tmp/llvm/lib' gmake: *** [all] Error 1...

Hi, after perusing through llc -debug output and stepping through the ARMGenDAGIsel.inc in the debugger, I would greatly like some help in tracking down a failing match to a pattern I specified: First, here is a snippet of a successful match (done in ARM mode) ISEL: Starting pattern match on root node: 0x1e7adf0: i32,ch = load 0x1e4c030, 0x1e78210, 0x1e78310<LD4[ConstantPool]...

...- > > eor r1, r1, #4294967295 ; and r0, r1, r0 > > On the surface it seems that the selector is not commuting the AND > operands. I've attached the complete test files. I can take a look > but I need a pointer to get started. No, isel is trying to commute the AND. See ARMGenDAGISel.inc (auto- generated by tablegen): // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>)) // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs) // Pattern complexity = 19 cost = 1 size = 0 { .. }...

...ssertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!"" failed: file "CodeGenDAGPatterns.cpp", line 932, function "ApplyTypeConstraints" gmake[3]: *** [/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM/Release/ARMGenDAGISel.inc.tmp] Abort trap (core dumped) gmake[3]: Leaving directory `/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM' gmake[2]: *** [ARM/.makeall] Error 2 gmake[2]: Leaving directory `/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target' gmake[1]: *** [Target/.makeall] Error 2 gmake[1]:...

...1, #4294967295 ; and r0, r1, r0 >> >> On the surface it seems that the selector is not commuting the AND >> operands. I've attached the complete test files. I can take a look >> but I need a pointer to get started. > > No, isel is trying to commute the AND. See ARMGenDAGISel.inc (auto- > generated by tablegen): > > // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, > (imm:i32)<<P:Predicate_immAllOnes>>)) > // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs) > // Pattern complexity = 19 cost = 1 size = 0 &...

...:0> <volatile> alignment=4 > Stack dump: > 0. Program arguments: llc -march=arm > 1. Running pass 'ARM Instruction Selection' on function > '@test_compare_and_swap' It's hard to guess what the problem is from this. Are you able to step through the code in ARMGenDAGISel.inc to see why it fails to match? Evan > > > I took a look at how the atomic_compare_swap implementation is done > for > PowerPC and X86 but got no clue how it gets from atomic_cmp_swap_32 to > the target specific variant. Well, for X86 its done via a custom > lowering. &...

Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) have similar patterns, as we would expect: defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: $RHS))>>; defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: $RHS))>>; Compiling the following three works as expected: %tmp1 = xor i32

Hi, Now that clang is warning about unused functions, the self-host build is really noisy. The majority of the unused functions are generated by TableGen: /Volumes/Data/b/lib/Target/ARM/ARMGenDAGISel.inc:643:13: warning: unused function 'Predicate_t2_so_imm2part' [-Wunused-function] inline bool Predicate_t2_so_imm2part(SDNode *inN) const { ^ Specifically this FIXME in DAGISelEmitter::run: // FIXME: These are being used by hand written code, gross. EmitPredicateFunction...

...> XXXISelDAGToDAG.cpp for all backends (XXX=X86, ARM, ...) > > The NOINLINE-macro after each method's argument list and right > before the "{" in the various lib/Target/XXX/XXXGenDAGISel.inc- > files seems to be the culprit, e.g. in llvm-build/lib/Target/ARM/ > ARMGenDAGISel.inc (line 145): Is this patch incorporated on the 1.8 branch? http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of- Mon-20060731/036455.html g.

Hello, Edd > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node > > type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function > > "ApplyTypeConstraints" Could you please try with gcc 4.x and check, whether

On Thu, Jun 12, 2008 at 11:41 AM, Anton Korobeynikov <asl at math.spbu.ru> wrote: > Hello, Edd > >> > llvm[3]: Building ARM.td instruction selector implementation with tblgen >> > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node >> > type!"" failed: file "CodeGenDAGPatterns.cpp", line

On 2008-06-10, at 09:19, Edd Barrett wrote: > I am a student considering a compiler design based dissertation with > llvm. I am having problems building llvm on OpenBSD-current. I hope > to make a port of llvm for OpenBSD once I have figured out how to > build it. Hi Edd, Could you please update to r52213 or later in svn and check whether this error is resolved with your

...getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node > type!"" failed: file "CodeGenDAGPatterns.cpp", line 932, function > "ApplyTypeConstraints" > gmake[3]: *** [/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM/Release/ARMGenDAGISel.inc.tmp] > Abort trap (core dumped) > gmake[3]: Leaving directory > `/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM' > gmake[2]: *** [ARM/.makeall] Error 2 > gmake[2]: Leaving directory > `/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target' > gmake[1]: *** [...

Hi, I have reworked my previous example and got something which is accepted by tblgen: let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def ARM_ATOMIC_CMP_SWAP : ABXI<0b1011, (outs GPR:$dst), (ins i32imm:$ptr, i32imm:$old, i32imm:$new), "do_something", [(set GPR:$dst, (atomic_cmp_swap_32

On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote: > ISDOpcodes.h contains what documentation there is on the semantics of each > opcode. And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in MachineInstr form, but you'll see them with -view-sched-dags, and occasionally before). Tim.

Hi, I am missing atomic operations support for the ARM backend (see PR #3887) and started trying to implement them. Since this is the first time that I work on such stuff (and llvm) I am going to take the supposedly easy route and provide an implementation that will work on Linux systems. This involves calling a special function which the kernel handles itself. Details here:

Hi David, > [(set GR32:$rD, globaladdr:$addr)] > It seems to have somehow managed to create a cycle in the DAG, which is > of course wrong. But how? When I write a similar pattern into the ARM .td files and look at (from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see: /*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494 /*56481*/ OPC_RecordNode, // #0 = $src /*56482*/ OPC_CheckType, MVT::i32, /*56484*/ OPC_CheckPatternPredicate, 4, // (!Subtarget->isThumb()) /*56486*/ OPC_MorphNodeTo, TARGET_VAL(ARM::MOVi3...

...itignore @@ -0,0 +1 @@ +DataTypes.h diff --git a/lib/Target/ARM/.gitignore b/lib/Target/ARM/.gitignore new file mode 100644 index 0000000..885bdf1 --- /dev/null +++ b/lib/Target/ARM/.gitignore @@ -0,0 +1,13 @@ +ARMGenAsmMatcher.inc +ARMGenAsmWriter.inc +ARMGenCallingConv.inc +ARMGenCodeEmitter.inc +ARMGenDAGISel.inc +ARMGenEDInfo.inc +ARMGenFastISel.inc +ARMGenInstrInfo.inc +ARMGenMCCodeEmitter.inc +ARMGenMCPseudoLowering.inc +ARMGenRegisterInfo.inc +ARMGenSubtargetInfo.inc +ARMGenDisassemblerTables.inc diff --git a/lib/Target/CellSPU/.gitignore b/lib/Target/CellSPU/.gitignore new file mode 100644 index 00...

Hi there, I am a student considering a compiler design based dissertation with llvm. I am having problems building llvm on OpenBSD-current. I hope to make a port of llvm for OpenBSD once I have figured out how to build it. Observe: llvm[3]: Compiling Deserialize.cpp for Release build In file included from /home/edd/llvm/llvm-2.3/include/llvm/Bitcode/BitstreamRead er.h:18, from