Displaying 6 results from an estimated 6 matches for "armgencodeemitter".
2011 Aug 30
2
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...fixed in the current svn head either as far as I can tell.)
1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
case ARM::VLDRD:
case ARM::VSTRD: {
// op: p
op = getMachineOpValue(MI, MI.getOperand(3));
Value |= (op & 15U) << 28;
// etc ...
Value = VFPThumb2PostEncoder(MI, Value); // <--- overwrites Value!
break;
}
The bug here is tha...
2011 Aug 30
0
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...tatic encoding, but the MCJIT is still in its infancy.
> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>
> case ARM::VLDRD:
> case ARM::VSTRD: {
> // op: p
> op = getMachineOpValue(MI, MI.getOperand(3));
> Value |= (op & 15U) << 28;
> // etc ...
> Value = VFPThumb2PostEncoder(MI, Value); // <--- overwrites Value!
>...
2011 Aug 30
2
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...ng that this one can be eliminated entirely."
>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>
>>
>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>> should be
>> Case += " Value |= " + PostEmitter + "(MI, Value);\n"...
2011 Aug 30
0
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...ng that this one can be eliminated entirely."
>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>
>>
>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>> should be
>> Case += " Value |= " + PostEmitter + "(MI, Value);\n...
2011 Aug 30
5
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...his one can be eliminated entirely."
>
>>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>>
>>>
>>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>>> should be
>>> Case += " Value |= " + PostEmitte...
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...include/llvm/Support/.gitignore
@@ -0,0 +1 @@
+DataTypes.h
diff --git a/lib/Target/ARM/.gitignore b/lib/Target/ARM/.gitignore
new file mode 100644
index 0000000..885bdf1
--- /dev/null
+++ b/lib/Target/ARM/.gitignore
@@ -0,0 +1,13 @@
+ARMGenAsmMatcher.inc
+ARMGenAsmWriter.inc
+ARMGenCallingConv.inc
+ARMGenCodeEmitter.inc
+ARMGenDAGISel.inc
+ARMGenEDInfo.inc
+ARMGenFastISel.inc
+ARMGenInstrInfo.inc
+ARMGenMCCodeEmitter.inc
+ARMGenMCPseudoLowering.inc
+ARMGenRegisterInfo.inc
+ARMGenSubtargetInfo.inc
+ARMGenDisassemblerTables.inc
diff --git a/lib/Target/CellSPU/.gitignore b/lib/Target/CellSPU/.gitignore
new file m...