search for: armgenasmmatch

Displaying 4 results from an estimated 4 matches for "armgenasmmatch".

Did you mean: armgenasmmatcher
2015 Sep 17
2
Register Number
Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7
2017 Dec 06
3
buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win
...ving side-effects. Instead, I’ve noticed that in the build log (http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6552/steps/build-unified-tree/logs/stdio), llvm-tblgen.exe is built (my patch modified it), but the table-generation steps of the main build (importantly, ARMGenAsmMatcher.inc) do not appear to be running. I think this would explain the FileCheck output from those failing tests. Could there be a buildbot misconfiguration which is preventing the newly-built llvm-tblgen from being used? Oliver From: Galina Kistanova [mailto:gkistanova at gmail.com] Sent: 04 Decemb...
2015 Sep 17
2
Register Number
On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote: > It seems like d0 is always 14! > I check it with ARMGenAsmMatcher.inc it was the same! > How is it possible? because it should give the same register value that > matches the underlying platform not any autogenerated value!? The returned number is the register id as defined in <YourTarget>GenRegisterInfo.inc. These numbers don't have any mean...
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...e new file mode 100644 index 0000000..1025214 --- /dev/null +++ b/include/llvm/Support/.gitignore @@ -0,0 +1 @@ +DataTypes.h diff --git a/lib/Target/ARM/.gitignore b/lib/Target/ARM/.gitignore new file mode 100644 index 0000000..885bdf1 --- /dev/null +++ b/lib/Target/ARM/.gitignore @@ -0,0 +1,13 @@ +ARMGenAsmMatcher.inc +ARMGenAsmWriter.inc +ARMGenCallingConv.inc +ARMGenCodeEmitter.inc +ARMGenDAGISel.inc +ARMGenEDInfo.inc +ARMGenFastISel.inc +ARMGenInstrInfo.inc +ARMGenMCCodeEmitter.inc +ARMGenMCPseudoLowering.inc +ARMGenRegisterInfo.inc +ARMGenSubtargetInfo.inc +ARMGenDisassemblerTables.inc diff --git a/lib...