search for: armfastisel

...lt;+44>: pop {r11, lr} 0x401e420c <+48>: bx lr blx instruction is available from ARM architecture v5 and above… After lot of investigations I found where llvm is generating this instruction : https://github.com/rust-lang/llvm/blob/168f91ce5cbf8933e47f339911f0f46a48714852/lib/Target/ARM/ARMFastISel.cpp#L2395 <https://github.com/rust-lang/llvm/blob/168f91ce5cbf8933e47f339911f0f46a48714852/lib/Target/ARM/ARMFastISel.cpp#L2395> UseReg variable is true causing ARMSelectCallOp function to set a BLX instruction that is not supported on armv4 :-( Could you help me to solve this ? Many thank...

...late it. The lower level IRs we currently use don't have that property. DAGs and MI refer back to LLVM IR. This creates some redundancy and makes serialization harder. It also creates problems when a pass wants to modify information that is in the llvm IR. For example, we have a memory leak in ARMFastISel.cpp:2194 :-( So the question is if the plan is to make MI a "complete" IR, that we can serialize independently of the LLVM IR, run a single pass on, etc. Thanks, Rafael

...9 or separate option could enable it from front-end (Clang in this case). I'm doing this for ARM platform and the flag should be reachable from all these places in LLVM: - lib/Analysis/ValueTracking.cpp - lib/CodeGen/SelectionDAG/SelectionDAG.cpp - lib/IR/ConstantFold.cpp - lib/Target/ARM/ARMFastISel.cpp - lib/Target/ARM/ARMISelLowering.cpp - lib/Target/ARM/ARMInstrVFP.td (through predicates) - lib/Target/ARM/ARMRegisterInfo.td (through predicates) and in Clang: - lib/AST/ExprConstant.cpp Did I get it right and there is no such flag so far? Does what I'm suggesting sounds reasonable...

...> 0x401e420c <+48>: bx lr > blx instruction is available from ARM architecture v5 and above… > > After lot of investigations I found where llvm is generating this instruction : > https://github.com/rust-lang/llvm/blob/168f91ce5cbf8933e47f339911f0f46a48714852/lib/Target/ARM/ARMFastISel.cpp#L2395 <https://github.com/rust-lang/llvm/blob/168f91ce5cbf8933e47f339911f0f46a48714852/lib/Target/ARM/ARMFastISel.cpp#L2395> > UseReg variable is true causing ARMSelectCallOp function to set a BLX instruction that is not supported on armv4 :-( > > Could you help me to solve this...

...example, createMemMoveLoop() doesn’t even use the alignments it’s given at all right now, and the neither of the createMemCpyLoop*() functions try to set the alignments on the loads & stores it creates. Passes that have conservative alignments after updating: - SelectionDAG - AArch64FastISel - ARMFastISel - MemorySanitizer - MemCpyOpt : Call slot optimization - InlineFunction : HandleByValArgumentInit - LowerMemIntrinsics (see note above) Cheers, Daniel --- Daniel Neilson, Ph.D. Azul Systems On Jan 2, 2018, at 2:11 PM, Daniel Neilson via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-d...

...t even use the alignments > it’s given at all right now, and the neither of the createMemCpyLoop*() > functions try to set the alignments on the loads & stores it creates. > > Passes that have conservative alignments after updating: > - SelectionDAG > - AArch64FastISel > - ARMFastISel > - MemorySanitizer > - MemCpyOpt : Call slot optimization > - InlineFunction :  HandleByValArgumentInit > - LowerMemIntrinsics (see note above) > > Cheers, >  Daniel > > --- > Daniel Neilson, Ph.D. > Azul Systems > > >> On Jan 2, 2018, at 2:11 PM, D...

...level IRs we currently use don't have that property. DAGs > and MI refer back to LLVM IR. This creates some redundancy and makes > serialization harder. It also creates problems when a pass wants to > modify information that is in the llvm IR. For example, we have a > memory leak in ARMFastISel.cpp:2194 :-( > > So the question is if the plan is to make MI a "complete" IR, that we > can serialize independently of the LLVM IR, run a single pass on, etc. Absolutely, although that project is somewhat orthogonal to the design of the instruction selector. Some back-referen...

...> > I'm doing this for ARM platform and the flag should be reachable from > all these places in LLVM: > > A - lib/Analysis/ValueTracking.cpp > A - lib/CodeGen/SelectionDAG/SelectionDAG.cpp > A - lib/IR/ConstantFold.cpp > A - lib/Target/ARM/ARMFastISel.cpp > A - lib/Target/ARM/ARMISelLowering.cpp > A - lib/Target/ARM/ARMInstrVFP.td (through predicates) > A - lib/Target/ARM/ARMRegisterInfo.td (through predicates) > > and in Clang: > > A - lib/AST/ExprConstant.cpp > > Did I get it right an...

Good day all, I’ve spent a few days resurrecting the circa-2015 work on removing the explicit alignment argument (4th arg) from the @llvm.memcpy/memmove/memset intrinsics in favour of using the alignment attribute on the pointer args of calls to the intrinsic. This work was first proposed back in August 2015 by Lang Hames: http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html (item

...ctionDAG/FunctionLoweringInfo.cpp | 4 +- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 14 ++-- lib/CodeGen/SelectionDAG/InstrEmitter.h | 2 +- lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | 16 ++--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 +-- lib/Target/ARM/ARMFastISel.cpp | 76 ++++++++++------------ lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/ARM/ARMISelLowering.h | 2 +- lib/Target/Mips/MipsISelLowering.cpp | 6 +- 13 files changed, 87 insertions(+), 78 deletions(-) commit 9add28389f...

...de/llvm/IR/Intrinsics.td > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > llvm/trunk/lib/IR/AutoUpgrade.cpp > llvm/trunk/lib/IR/IRBuilder.cpp > llvm/trunk/lib/IR/Verifier.cpp > llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp > llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > llvm/trunk/lib/Target/Mips/MipsFastISel.cpp > llvm/trunk/lib/Target/X86/X86FastISel.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp > llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp > llvm/trunk/test/Analysis/AliasSet/memtransfer.ll &g...

...rm and the flag should be reachable from > >> all these places in LLVM: > >> > >> A - lib/Analysis/ValueTracking.cpp > >> A - lib/CodeGen/SelectionDAG/SelectionDAG.cpp > >> A - lib/IR/ConstantFold.cpp > >> A - lib/Target/ARM/ARMFastISel.cpp > >> A - lib/Target/ARM/ARMISelLowering.cpp > >> A - lib/Target/ARM/ARMInstrVFP.td (through predicates) > >> A - lib/Target/ARM/ARMRegisterInfo.td (through predicates) > >> > >> and in Clang: > >> > >> A - lib/...

...nclude/llvm/IR/Intrinsics.td<http://rinsics.td/> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/...

I am hoping that this proposal will generate a lot of feedback, and there are many different topics to discuss. When replying to this email, please change the subject header to something more specific, but keep the [global-isel] tag. Thanks, /jakob Proposal for a Global Instruction Selector It is becoming evident that we need a replacement for the SelectionDAG-based instruction selector. This

...>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp >> llvm/trunk/lib/IR/AutoUpgrade.cpp >> llvm/trunk/lib/IR/IRBuilder.cpp >> llvm/trunk/lib/IR/Verifier.cpp >> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp >> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp >> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp >> llvm/trunk/lib/Target/X86/X86FastISel.cpp >> llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp >> llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp >> llvm/trunk/test/Analysis/AliasS...

...nk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp >>> llvm/trunk/lib/IR/AutoUpgrade.cpp >>> llvm/trunk/lib/IR/IRBuilder.cpp >>> llvm/trunk/lib/IR/Verifier.cpp >>> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp >>> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp >>> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp >>> llvm/trunk/lib/Target/X86/X86FastISel.cpp >>> llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp >>> llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp >>> llvm/trunk/...

...nclude/llvm/IR/Intrinsics.td<http://rinsics.td/> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/...

...nclude/llvm/IR/Intrinsics.td<http://rinsics.td/> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/...