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I'm doing some tests running llvm on Android. I'm getting an error message saying: Unhandled instruction encoding format! I checked which instruction was causing this and it is ADDrsi, it appears to have format 42 << 7, which is definitely not available in ARMBaseInfo.h Any suggestions are welcome -- Guillermo A. Pérez (吉耶莫) -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120220/dfd55f45/attachment.html>

Dear Tim, Thank you for your thorough reply. So, based on your reply I get every operand and check them to be (isDef && !isimplicit). Now my problem is that it gives me the physical register number.i.e, for example, instead of r0, it return %physreg66. Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank

...Android. I'm getting an error message > saying:**** > > ** ** > > Unhandled instruction encoding format!**** > > ** ** > > I checked which instruction was causing this and it is ADDrsi, it appears > to have format 42 << 7, which is definitely not available in ARMBaseInfo.h > **** > > ** ** > > Any suggestions are welcome > **** > > ** ** > > -- > Guillermo A. Pérez (吉耶莫)**** > -- Guillermo A. Pérez (吉耶莫) -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-de...

...LVMdev] ARM opcode format I'm doing some tests running llvm on Android. I'm getting an error message saying: Unhandled instruction encoding format! I checked which instruction was causing this and it is ADDrsi, it appears to have format 42 << 7, which is definitely not available in ARMBaseInfo.h Any suggestions are welcome -- Guillermo A. Pérez (吉耶莫) -- Guillermo A. Pérez (吉耶莫) -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclos...

...Android. I'm getting an error message > saying:**** > > **** > > Unhandled instruction encoding format!**** > > **** > > I checked which instruction was causing this and it is ADDrsi, it appears > to have format 42 << 7, which is definitely not available in ARMBaseInfo.h > **** > > **** > > Any suggestions are welcome > **** > > **** > > -- > Guillermo A. Pérez (吉耶莫)**** > > > > **** > > ** ** > > -- > Guillermo A. Pérez (吉耶莫)**** > > -- IMPORTANT NOTICE: The contents of this email and any attach...