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...uence how those cores get scheduled and preempted, I don't think there's any hope that the compiler can do a good job at predicting usage or having any real impact amidst higher level latency, such as context switches and systemcalls. -- cheers, --renato [1] https://en.wikipedia.org/wiki/ARM_big.LITTLE

Hey, I've been reading back the thread and there's a lot of ideas flying around, I may have missed more than I should, but here's my view on it. First, I think this is a good idea. Mapping caches is certainly interesting to general architectures, but particularly important to massive operations like matrix multiply and stencils can pull a lot of data into cache and sometimes thrash