Displaying 20 results from an estimated 31 matches for "arm_aapcscc".
2012 Aug 06
2
[LLVMdev] ARM eabi calling convention
...ar **argv) {
S0 s0 = { 2.0 };
foo0(1, s0);
printf("%f\n", g1.d);
* * return 0;
}*
with this command,
*$ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7
-emit-llvm vararg1-main.c -S -o vararg1-main.ll -O3*
I get this bitcode.
*$ cat vararg1-main.ll
define arm_aapcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
entry:
%0 = load [2 x i32]* bitcast (%struct.S0* @main.s0 to [2 x i32]*), align 8
tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0)
nounwind
%1 = load double* getelementptr inbounds (%struct.S0* @g1, i32 0, i32 0),
align 8...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
Yes, I see the load is 8-byte aligned in the bit code.
My question was, assuming that arguments requiring double word alignment
have to be passed in even/odd registers, how does the backend know that %0
has to be passed in register r2 and r3?
*tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0)
nounwindt
*
It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
originally a structure consisting of a single double field. When I run llc,
it looks like "%0" is being passed in register r1 and r2.
*$ llc vara...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
..."%f\n", g1.d);
>
> return 0;
> }
>
> with this command,
>
> $ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7 -emit-llvm vararg1-main.c -S -o vararg1-main.ll -O3
>
> I get this bitcode.
>
> $ cat vararg1-main.ll
>
> define arm_aapcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
> entry:
> %0 = load [2 x i32]* bitcast (%struct.S0* @main.s0 to [2 x i32]*), align 8
> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwind
> %1 = load double* getelementptr inbounds (%struct.S0* @g1, i3...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
...> wrote:
> Yes, I see the load is 8-byte aligned in the bit code.
>
> My question was, assuming that arguments requiring double word alignment
> have to be passed in even/odd registers, how does the backend know that %0
> has to be passed in register r2 and r3?
>
> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt
>
> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
> originally a structure consisting of a single double field. When I run llc,
> it looks like "%0" is being passed in register r1 an...
2012 Jul 05
2
[LLVMdev] Vector argument passing abi for ARM ?
...r instance is this valid to write .ll statement like:
; ModuleID = 'bugconv.ll'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "thumbv7-none-linux-androideabi"
define arm_aapcscc void @bugtest_CALL(i8* nocapture %.T_0375) nounwind {
L.entry:
%0 = bitcast i8* %.T_0375 to <2 x i8>*
%1 = load <2 x i8>* %0, align 2
%2 = getelementptr i8* %.T_0375, i32 2
%3 = bitcast i8* %2 to <2 x i8>*
%4 = load <2 x i8>* %3, align 2
tail call arm_aapcscc vo...
2012 Jul 05
2
[LLVMdev] RE : Vector argument passing abi for ARM ?
...ample to reproduce the problem I'm experiencing:
; ModuleID = 'bugparam.ll'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "thumbv7-none-linux-androideabi"
define arm_aapcscc void @bar(i8* nocapture %.T0352, i16* nocapture %p) {
L.entry:
%0 = load i16* %p, align 2
%1 = bitcast i16 %0 to <2 x i8>
%2 = getelementptr i16* %p, i32 1
%3 = load i16* %2, align 2
%4 = bitcast i16 %3 to <2 x i8>
tail call arm_aapcscc void @zzz(<2 x i8> %1, <2 x...
2011 Oct 18
2
[LLVMdev] LLVM constant propagation optimization question
Hi all,
I'm writting following LLVM assembly:
; ModuleID = 'structaccess.ll'
%struct._anon0 = type <{ i32, i32, i32 }>
@s = common global %struct._anon0 zeroinitializer
define arm_aapcscc void @foo() nounwind {
L.entry:
store i32 5, i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32
0)
store i32 10, i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32
1)
%0 = load i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32 0)
%1 = load i32* getelementptr inbo...
2012 Jul 05
3
[LLVMdev] Vector argument passing abi for ARM ?
...l statement like:
>
> ; ModuleID = 'bugconv.ll'
> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
> i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
> target triple = "thumbv7-none-linux-androideabi"
>
> define arm_aapcscc void @bugtest_CALL(i8* nocapture %.T_0375) nounwind
> {
> L.entry:
> %0 = bitcast i8* %.T_0375 to <2 x i8>*
> %1 = load <2 x i8>* %0, align 2
> %2 = getelementptr i8* %.T_0375, i32 2
> %3 = bitcast i8* %2 to <2 x i8>*
> %4 = load <2 x i8>* %3,...
2011 Oct 18
3
[LLVMdev] LLVM constant propagation optimization question
...tructaccess.ll'
> >
>
> not having a data layout string in your module disables many optimizations.
>
> Ciao, Duncan.
>
> > %struct._anon0 = type <{ i32, i32, i32 }>
> >
> > @s = common global %struct._anon0 zeroinitializer
> >
> > define arm_aapcscc void @foo() nounwind {
> > L.entry:
> > store i32 5, i32* getelementptr inbounds (%struct._anon0* @s, i32 0,
> i32 0)
> > store i32 10, i32* getelementptr inbounds (%struct._anon0* @s, i32 0,
> i32 1)
> > %0 = load i32* getelementptr inbounds (%struct._anon0*...
2012 Jul 05
0
[LLVMdev] RE : Vector argument passing abi for ARM ?
...em I'm experiencing:
>
> ; ModuleID = 'bugparam.ll'
> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
> target triple = "thumbv7-none-linux-androideabi"
>
> define arm_aapcscc void @bar(i8* nocapture %.T0352, i16* nocapture %p) {
> L.entry:
> %0 = load i16* %p, align 2
> %1 = bitcast i16 %0 to <2 x i8>
> %2 = getelementptr i16* %p, i32 1
> %3 = load i16* %2, align 2
> %4 = bitcast i16 %3 to <2 x i8>
> tail call arm_aapcs...
2012 Jul 05
0
[LLVMdev] Vector argument passing abi for ARM ?
...>> ; ModuleID = 'bugconv.ll'
>> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
>> i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
>> target triple = "thumbv7-none-linux-androideabi"
>>
>> define arm_aapcscc void @bugtest_CALL(i8* nocapture %.T_0375) nounwind
>> {
>> L.entry:
>> %0 = bitcast i8* %.T_0375 to <2 x i8>*
>> %1 = load <2 x i8>* %0, align 2
>> %2 = getelementptr i8* %.T_0375, i32 2
>> %3 = bitcast i8* %2 to <2 x i8>*
>>...
2012 Jun 25
2
[LLVMdev] Is llc broken for Cortex-A9 + neon ?
Hi all,
considering following .ll file
; ModuleID = 'vect3x.ll'
target triple = "armv7-none-linux-gnueabi"
define arm_aapcscc void @test_hi_char8(i8* %.T0351, <8 x i8>* nocapture %srcA, <4 x i8>* nocapture %dst) noinline {
L.entry:
%0 = tail call arm_aapcscc i32 (...)* @get_global_id(i8* %.T0351, i32 0)
%1 = bitcast <8 x i8>* %srcA to <4 x i8>*
%2 = getelementptr <4 x i8>* %1, i32 0, i...
2011 Oct 18
0
[LLVMdev] LLVM constant propagation optimization question
...llowing LLVM assembly:
>
> ; ModuleID = 'structaccess.ll'
>
not having a data layout string in your module disables many optimizations.
Ciao, Duncan.
> %struct._anon0 = type <{ i32, i32, i32 }>
>
> @s = common global %struct._anon0 zeroinitializer
>
> define arm_aapcscc void @foo() nounwind {
> L.entry:
> store i32 5, i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32 0)
> store i32 10, i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32 1)
> %0 = load i32* getelementptr inbounds (%struct._anon0* @s, i32 0, i32 0)
> %1 =...
2012 Jul 05
0
[LLVMdev] Vector argument passing abi for ARM ?
...r instance is this valid to write .ll statement like:
; ModuleID = 'bugconv.ll'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "thumbv7-none-linux-androideabi"
define arm_aapcscc void @bugtest_CALL(i8* nocapture %.T_0375) nounwind {
L.entry:
%0 = bitcast i8* %.T_0375 to <2 x i8>*
%1 = load <2 x i8>* %0, align 2
%2 = getelementptr i8* %.T_0375, i32 2
%3 = bitcast i8* %2 to <2 x i8>*
%4 = load <2 x i8>* %3, align 2
tail call arm_aapcscc vo...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...e the load is 8-byte aligned in the bit code.
>>
>> My question was, assuming that arguments requiring double word alignment
>> have to be passed in even/odd registers, how does the backend know that %0
>> has to be passed in register r2 and r3?
>>
>> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt
>>
>> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
>> originally a structure consisting of a single double field. When I run llc,
>> it looks like "%0" is being passed...
2012 Jun 25
0
[LLVMdev] Is llc broken for Cortex-A9 + neon ?
...illa and assign to Nadav.
On Mon, Jun 25, 2012 at 5:04 PM, Sebastien DELDON-GNB
<sebastien.deldon at st.com> wrote:
> Hi all,
>
>
> considering following .ll file
>
> ; ModuleID = 'vect3x.ll'
> target triple = "armv7-none-linux-gnueabi"
>
> define arm_aapcscc void @test_hi_char8(i8* %.T0351, <8 x i8>* nocapture %srcA, <4 x i8>* nocapture %dst) noinline {
> L.entry:
> %0 = tail call arm_aapcscc i32 (...)* @get_global_id(i8* %.T0351, i32 0)
> %1 = bitcast <8 x i8>* %srcA to <4 x i8>*
> %2 = getelementptr <4 x i8&...
2012 Sep 21
2
[LLVMdev] ARM aapcs calling convention for small vectors
Hi all,
I was wondering if ARM aapcs calling convention defines how to pass small vectors as parameter to a routine.
By small vectors, I mean with size less than a 32-bit integer. For instance if we consider following code:
; ModuleID = 'smallvect.ll'
define arm_aapcscc void @foo(<2 x i8>* %p) {
L.entry:
%0 = load <2 x i8>* %p
call arm_aapcscc void @bar(<2 x i8> %0)
ret void
}
declare arm_aapcscc void @bar(<2 x i8> %a)
and we compile it using llc -march=arm -mcpu=cortex-a9 we got following assembly generated:
...
foo:...
2012 Jun 25
2
[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?
...illa and assign to Nadav.
On Mon, Jun 25, 2012 at 5:04 PM, Sebastien DELDON-GNB
<sebastien.deldon at st.com> wrote:
> Hi all,
>
>
> considering following .ll file
>
> ; ModuleID = 'vect3x.ll'
> target triple = "armv7-none-linux-gnueabi"
>
> define arm_aapcscc void @test_hi_char8(i8* %.T0351, <8 x i8>* nocapture %srcA, <4 x i8>* nocapture %dst) noinline {
> L.entry:
> %0 = tail call arm_aapcscc i32 (...)* @get_global_id(i8* %.T0351, i32 0)
> %1 = bitcast <8 x i8>* %srcA to <4 x i8>*
> %2 = getelementptr <4 x i8&...
2016 May 12
3
Why LR is saved before calling a 'noreturn' function ?
...e noreturn
$ clang --target=arm -S -emit-llvm -O1 noreturn.c -o noreturn.ll && cat noreturn.ll
; ModuleID = 'noreturn.c'
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv4t--"
; Function Attrs: noreturn nounwind
define arm_aapcscc void @foo(i32* %a) #0 {
entry:
tail call arm_aapcscc void @bar(i32* %a) #2
unreachable
}
; Function Attrs: noreturn
declare arm_aapcscc void @bar(i32*) #1
attributes #0 = { noreturn nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" &quo...
2010 Oct 19
2
[LLVMdev] Structure memory layout
...:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
3 target triple = "armv5-none-linux-gnueabi"
4
5 %0 = type { i8, i8 }
6 %struct.test = type <{ i8, i8 }>
7
8 @vm = global %0 { i8 17, i8 11 } ; <%0*> [#uses=1]
9
10 define arm_aapcscc i32 @main() nounwind {
11 entry:
12 %retval = alloca i32 ; <i32*> [#uses=1]
13 %a = alloca i32 ; <i32*> [#uses=0]
14 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
15 %0 = load i8*...