search for: arm926ej

Hi all, I'm trying to use libspeex 1.1.10 on an ARM926EJ-Sid(wb) rev 3 (v5l). I executed the speexenc and speexdec test files and they can encode and decode. But I'm getting 95% of cpu utilization on the codification and 44% on the decodification. I saw in the post: http://lists.xiph.org/pipermail/speex-dev/2005-June/003485.html that this version...

...ip that's at least twice slower than yours with the > settings you're using. > > Jean-Marc > > Le jeudi 15 septembre 2005 ? 16:23 -0400, Eduardo Bezerra a ?crit : > > Hi all, > > > > > > > > I'm trying to use libspeex 1.1.10 on an ARM926EJ-Sid(wb) rev 3 > > (v5l). I executed > > the speexenc and speexdec test files and they can encode and decode. > > But I'm getting 95% of cpu utilization on the codification and 44% on > > the decodification. > > I saw in the post: > > http://lists.xiph.org/p...

...I've had the encoder running in real-time on a chip that's at least twice slower than yours with the settings you're using. Jean-Marc Le jeudi 15 septembre 2005 ? 16:23 -0400, Eduardo Bezerra a ?crit : > Hi all, > > > > I'm trying to use libspeex 1.1.10 on an ARM926EJ-Sid(wb) rev 3 > (v5l). I executed > the speexenc and speexdec test files and they can encode and decode. > But I'm getting 95% of cpu utilization on the codification and 44% on > the decodification. > I saw in the post: > http://lists.xiph.org/pipermail/speex-dev/2005-June/0...

Hi, I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. Here is output: # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) Target: arm-unknown-freebsd Thread model: posix "/opt/llvm/bin/clang" -cc1 -triple armv5e-unknown-freebsd -S -disable-free -main-file-name rrx.c -mrelocation-mo...

...results before I continue. Brief version: WB decode takes ~24MIPS, encode takes ~243MIPS. NB decode takes ~10MIPS, encode takes ~102MIPS. (And by MIPS, I mean ARM CPU cycles, not Dhrystone MIPS) If I manually (because I couldn't figure out how to make configure do it) add "-mpcu=arm926ej_s" and "-DSHORTCUTS", the wideband numbers drop to 22MIPS and 219MIPS, respectively. More Details: The commands/options I used to config Speex: # export ARM_INSTALL_TREE=/extern/toddk/workdir/filesys export CC=arm_v5t_le-gcc export CXX=arm_v5t_le-g++ export AR=arm_v5t_...

...Sharp SL-5500 (Collie) PDA (SA-1110) > connex Gumstix Connex (PXA255) > cubieboard cubietech cubieboard > highbank Calxeda Highbank (ECX-1000) > imx25-pdk ARM i.MX25 PDK board (ARM926) > integratorcp ARM Integrator/CP (ARM926EJ-S) > kzm ARM KZM Emulation Baseboard (ARM1136) > lm3s6965evb Stellaris LM3S6965EVB > lm3s811evb Stellaris LM3S811EVB > mainstone Mainstone II (PXA27x) > midway Calxeda Midway (ECX-2000) > musicpal Marvell 88w...

In the help command when i checked the processors supported by llvm 2.9 it showed arm926ej-s. which means thumb mode is supported right? this belongs to armv5. but the llvm documentation says thumb mode is supported only for armv6 and higher.. does it mean there is only a partial support for this processor? -------------- next part -------------- An HTML attachment was scrubbed... URL: &...

Hi > I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. > > Here is output: > > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) > Target: arm-unknown-freebsd > Thread model: posix >  "/opt/llvm/bin/clang" -cc1 -triple armv5e-unknown-freebsd It seems you're generating arm...

On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c Even though you specified cpu as arm9, it's probably generating generic ARM IR (use -emit-llvm -S and see), which defaults to ARM instructions. If you want thumb, use triple = thumb-unknown-freebsd, but still, that will have problems. You can do it in two...

Hi, I'm trying to get speex working on an ARM board (ARM926EJ-Sid(wb) core, ARM 5TE architecture) and getting segfaults if build with "--enable-fixed-point --enable-arm5e-asm" options. If I use just "--enable-fixed-point", then it runs fine, but once I add "--enable-arm5e-asm" it start crashing (I use testenc to test it). Furthe...

...ect, NUT is only designed to work with the libusb-0.1 API (provided by libusb-compat). > > I could not fing any more solution of that. Therefore, I turn to > developers. config.log is attached. Here are my hardware and > software configurations: > CPU: Marvell 88E6281 with ARM926ejs > Linux ver: 2.6.31.8 > cinfigure commnd: > ./configure --with-usb --with-doc \ > --host=arm-mv5sft-linux-gnueabi \ > --prefix=/mnt/ARM_FS \ > How did you install libusb-1.0? It appears that the actual .so file was not installed properly: configure:7259: checking for libusb ve...

Well how about as a strawman... taking some options from http://en.wikipedia.org/wiki/List_of_ARM_microprocessor_cores and http://en.wikipedia.org/wiki/List_of_applications_of_ARM_cores LLVM Supports: ARMv4T -> ARM7TDMI ARMv5TE -> ARM926EJ-S -> XScale ARMv6 -> ARM1136J(F)-S ARMv6ZK -> ARM1176JZ(F)-S ARMv7A -> Cortex-A8 Cortex-A9 ARMv7M -> Cortex-M3 Granted there are many many more listed within in ARM.td, but I think we should start with a small subset and build on it as we begin guaranteeing ma...

...f you only enable arm4 assembly? Also, if you can do some investigation, it would be useful to check what bit of assembly is causing the crash. Can you disable one at a time and check? Jean-Marc Alexander Chemeris a ?crit : > Hi, > > I'm trying to get speex working on an ARM board (ARM926EJ-Sid(wb) core, > ARM 5TE architecture) and getting segfaults if build with "--enable-fixed-point > --enable-arm5e-asm" options. If I use just "--enable-fixed-point", then > it runs fine, but once I add "--enable-arm5e-asm" it start crashing > (I use testenc...

Erik de Castro Lopo wrote: >> Currently, compression settings are as follows >> >> -6, -l 8 -b 4096 -m -r 6-A tukey(0.5) >> -7, -l 8 -b 4096 -m -e -r 6-A tukey(0.5) >> -8, -l 12 -b 4096 -m -e -r 6-A tukey(0.5) >> >> I suggest the following, in case my previous patch is accepted >> >> -6, -l 8 -b 4096 -m -r 6 -A tukey(0.5);partial_tukey(2)

...one with changing this too. > > Any thoughts? From <http://www.rockbox.org/wiki/CodecPerformanceComparison> it seems that the decoding of -8 is about 6% slower than -5. Sometimes the difference is bigger but doesn't exceed 10%. The only exception is "Freescale i.MX21 (454MHz ARM926EJ?-S, Fuze+)": 43x vs 35x realtime. But the decoding time is so small (4 sec vs 5 sec) that it can be some measurement error.

Hi masters, I am trying to deploy theora in Fressacle iMX27 (ARM-9) processor. This hardware does not support floating point operations, i've compiled the libtheora with ?--disable-float option . mx27# cat /proc/cpuinfo Processor ? ? ? : ARM926EJ-S rev 4 (v5l) BogoMIPS ? ? ? ?: 199.06 Features ? ? ? ?: swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant ? ? : 0x0 CPU part ? ? ? ?: 0x926 CPU revision ? ?: 4 Cache type ? ? ?: write-back Cache clean ? ? : cp15 c7 ops Cache lockdown ?: format C Cache form...

On Jun 22, 2011, at 3:16 PM, Renato Golin wrote: > On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: >> # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > > Even though you specified cpu as arm9, it's probably generating > generic ARM IR (use -emit-llvm -S and see), which defaults to ARM > instructions. > > If you want thumb, use triple = thumb-unknown-freebsd, but still, that > will h...

On Thu, Oct 13, 2011 at 11:25 AM, Joe Abbey <jabbey at arxan.com> wrote: > LLVM Supports: > ARMv4T  -> ARM7TDMI > ARMv5TE -> ARM926EJ-S >         -> XScale > ARMv6   -> ARM1136J(F)-S > ARMv6ZK -> ARM1176JZ(F)-S > ARMv7A  -> Cortex-A8 >            Cortex-A9 > ARMv7M  -> Cortex-M3 Does the LLVM code generator generate Thumb code in addition to ARM code? For those who don't know ARM, Thumb is a...

Hi Fellows, The goal is to find the induction variable for a loop, where the induction variable increments with the multiplication, division or shift operations, like this one: sz = 8; do { ... ... sz = sz / 2; } while (sz) Is SCEV capable of detecting the induction variable 'sz' in this case? The code snippet I am using to solve the problem is for each basic-block in a

> The ARM Holdings emulator does this; I used it with great success to > profile an Advanced Encryption Standard encryptor a while back. It is indeed a useful piece of kit. We do a lot of our internal regression tests on it, and also run LLVM's regression tests every night on it (as well as PlumHall, EEMBC and SpecInt). Unfortunately it's not exactly software we can give away or