search for: arm7tdmi

Dear ML, Anton, Thank you for your answer and your help. I had a look at ARM.td of LLVM 2.6 (in lib/Target/ARM..) where I found following definitions: // V4T Processors. def : ProcNoItin<"arm7tdmi", [ArchV4T]>; def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; def : ProcNoItin<"arm710t", [ArchV4T]>; def : ProcNoItin<"arm720t", [ArchV4T]>; def : ProcNoItin<"arm9", [ArchV4T]>; def : ProcNoIt...

Dear Anton, Thank you again for your help! I tried with the following options (adding --with-cpu=arm7tdmi and using binutils from cvs snapshot): ../llvm-gcc4.2-2.6.source/configure --prefix=/usr/local/cross-llvm-gcc-arm-elf-4.2-2.6 --program-prefix=llvm- --enable-llvm=/Users/dummy/Develop/llvm/llvm-build --enable-languages=c,c++ --host=i686-apple-darwin9 --build=i686-apple-darwin9 --target=arm-elf --w...

...Including DSP Instruction Set ? Built-in Floating-Point Processing Unit (FPU) ? Read-Modify-Write Instructions and Atomic Bit Manipulation ? Performing 1.49 DMIPS / MHz ? Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State) ? Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State) Or An ARM7TDMI core running at ~50Mhz for a narrow band 8Kbps sampling rate? I need to know this before I get deeper into Speex. Thanks a lot! Dominic Bazinet

...with -mthumb --target=arm-linux-androideabi -mcpu=cortex-a7, this records a triple of thumbv7a-linux-androideabi in the bitcode file. - The command line for the link step only passes --target= arm-linux-androideabi. - The default cpu passed to LTO for a triple arm-linux-androideabi is the very old arm7tdmi. - When the ARMAsmBackend is created from the combination of triple thumbv7a-linux-androideabi and cpu arm7tdmi the resultant target features only include Thumb1. Amongst other things this prevents MC from widening branch instructions to the Thumb2 wide branch. - Code generation prior to MC seems t...

Hello, Pazzo > Any clue? Yes. Sorry, my fault - next time I should check ARM docs before replying. ARM7TDMI is ARMv4T and this is not supported by LLVM (LLVM does v5+ codegen). -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hi, I'm evaluating the libspeex library for usage in an embedded platform based on an ARM7 TDMI micro (the ubiquitous Atmel AT91SAM7S). In details, I'm trying to use libspeex to encode the audio stream coming into the micro from an I2S channel and saving the encoded audio to an SD card (currently in binary format just to test it decoded back to the I2S channel from the saved file), but

...m-linux-androideabi -mcpu=cortex-a7, > this records a triple of thumbv7a-linux-androideabi in the bitcode file. > - The command line for the link step only passes --target= > arm-linux-androideabi. > - The default cpu passed to LTO for a triple arm-linux-androideabi is > the very old arm7tdmi. > - When the ARMAsmBackend is created from the combination of triple > thumbv7a-linux-androideabi and cpu arm7tdmi the resultant target > features only include Thumb1. Amongst other things this prevents MC > from widening branch instructions to the Thumb2 wide branch. > - Code gener...

Dear Anton, Thanks for your help! I had a look to llvm (2.6) configure options but I couldn't find any way to specify cpu type, fpu ecc..Could you please give me any indication and/or example? I want to try llvm with Atmel's AT91SAM7X256 (core is ARM7TDMI ) Thank you again, pz 2010/1/9 Anton Korobeynikov <anton at korobeynikov.info>: > Hello > >> But I got the followings errors: >> >> /var/folders/7f/7fiRIEm-FruFfT7mGbk3uk+++TI/-Tmp-//ccDFjySd.s: >> Assembler messages: >> /var/folders/7f/7fiRIEm-FruFfT7mG...

Well, it's an ARM7TDMI core, so basically one register operation per clock, with memory accesses taking longer. Having the memory on-chip should make memory access much less of an impact. I was afraid that you would answer the way you did: I thought about my question after I sent it, and the "LP" in CELP is w...

...cpu type, fpu ecc.. These are not llvm configure options, but gcc's one. Basically, you should configure llvm-gcc in the same way you do for gcc for your platform. > Could you please give me any > indication and/or example? I want to try llvm with Atmel's > AT91SAM7X256 (core is  ARM7TDMI ) I think adding --with-cpu=arm7tdmi to llvm-gcc configure should work -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hello, I'm sorry if this is not the correct place to ask this question but what I'm looking for is any data on the reality of Speex working on an ARM7 core? I'm looking at doing a few diffrent projects where I will be using a proc such as the LPC2378 with the ARM7TDMI-S core running at 72Mhz (although errata show only 60Mhz is currenlty possible). Do you know if there is a port that will work on this core? Thanks,Brett _________________________________________________________________ Connect to the next generation of MSN Messenger? http://imagine-msn.com/me...

I have to define a project that will have speex in the future. Can someone give me information about Speex running on an ARM7TDMI(v4) such as AT91SAM7S64? I will expect to use AEC, AGC noise reduction, encode and decode. Is this supposed to run? Or do I need something faster or different? Just for information: the chip runs at 55MHz, 1 wait stat in 32 bit mode or 0 wait in thumb mode. I intend to use a 16 bit codec such...

...then. So another question: - Is there a difference of performance/quality between the floating point and the fixed point? Actually, what's the main difference? Thanks again. Dominic Quoting Jean-Marc Valin <jmvalin at jmvalin.ca>: > I don't know the AVR32 chip. However for an ARM7TDMI running at 50 MHz, > assuming a good compiler and some hand-coded assembly, you would be very > close to the achievable limit (couldn't say on which side). So if your > AVR32 is faster than an ARM7TDMI, it's likely achievable. If it's > slower, then it's likely not achie...

I don't know the AVR32 chip. However for an ARM7TDMI running at 50 MHz, assuming a good compiler and some hand-coded assembly, you would be very close to the achievable limit (couldn't say on which side). So if your AVR32 is faster than an ARM7TDMI, it's likely achievable. If it's slower, then it's likely not achievable. Hope that he...

Hello All. Could anybody help me with one question about CELT? I develop one project based on ARM7TDMI or Cortex C3 core. Can i use CELT with 32kHz and 48kB on these fixed point cores? Or it`s need to transfer project to Blackfin core (but it isn`t convenient to me)? With best regards, Alexey Voroshen.

Hi, I wanted to know if it was possible to force ARM backend to compile a function in ARM while the rest is in Thumb mode. I tried the attributes which is used in GCC but it doesn't work. Here is what I tried: https://pastebin.com/jCr5LPUY Thanks in advance, Uvekilledkenny -------------- next part -------------- An HTML attachment was scrubbed... URL:

...an embedded system built around an ARM microcontroller. I have seen other posts indicating that Speex can run in real-time on some iPAQ PDA's, but these are using a StrongARM 166MHz processor. I'm looking more at the chips from Atmel (SAM7), Philips (LPC2xxx), and TI (TMS 470), which are ARM7TDMI with on-chip SRAM and flash, running at speeds of 33 to 60MHz. 166 down to 60 is a big drop, but I'm hoping to gain performance due to lack of wait states (no external memory), and the lack of any O/S running to eat cycles; the chip will only be encoding Speex. Still, it may not be enough. I...

Hi, all, I am porting speex on ARM7TDMI, I have done some optimization, the result is that the encoder and decoder need about 60 MCPS for 5.96kbps bitrate and complexity 0. Can someone give me informtion about Speex optimization on ARM7? Another question, my ADC and DAC are 12 bits, but Speex codec is 16bits, Did someone try to modify s...

...vm bitcode using: llvm-gcc -emit-llvm -c part1.c -o part1.bc llvm-gcc -emit-llvm -c part2.c -o part2.bc Then I link them together: llvm-ld part1.bc part2.bc -o combined.bc Now I use the ARM backend via llc to generate the assembly for my target processor from combined.bc: llc -march=arm -mcpu=arm7tdmi combined.bc The problem is when I run the generated file (combined.s) through an arm cross compiler for my target (arm-elf gcc toolchain) I get the following errors below. Has anybody encountered this before? Is there a way to do this? combined.s: Assembler messages: combined.s:216: rd and...

Compared to todays PDAs the GameBoy Advance (GBA) is low spec. it has a 16MHz ARM7tdmi RISC processor. 32-bit but it can handle 16-bit instructions in a mode that resembles "bytecode" (a 32-bit instruction is executed using a 16-bit instruction). I got a feeling that the GBA would need a FPU. For more information on the GBA visit this info page: http://www.cs.rit.edu/~tj...