Displaying 3 results from an estimated 3 matches for "arithlogicr".
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
...\
MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc
I get an error.
Included from
/home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474:
/home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1:
error: Duplicate record in FastISel table!
def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0,
0x2e>;
^
make[3]: ***
[/home/rkotler/llvmw/build/lib/Target/Mips/Debug+Asserts/MipsGenFastISel.inc.tmp]
Error 1
Then it creates a blank file for MipsGenFastISel.inc and after that I
get no build errors.
I'm not sure wha...
2015 Nov 23
3
Qs about TwoOperandAliasConstraint and TIED_TO
in llvm-3.6.2.src
1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file,
let TwoOperandAliasConstraint = "$dst = $rs1" in {
}
I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction,
the question is what am I doing wrong ?
2. I've noticed that TwoOperandAliasConstraint
2012 Sep 14
0
[LLVMdev] Seperating registers in target description string replacement without adding whitespace?
Here's an example piece of code to show you what I'm trying to do (on llvm
3.1):
class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")),
[(set RC...