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2009 Jul 06
1
[LLVMdev] Mips -> DLX Modifications as Target
...have been working on a DLX Target for LLVM using the
Mips Target as a base.
Coming along quite well, currently ran into two problems with my
sample/test program.
The main issue I am having is with respect to the following
(Note: I have already changed ADDui from ADDiu)
We have this
def ADDui : ArithI<0x09, "addui", add, simm16, immSExt16>;
However sticky speaking this should be in dlx the instructions are
addui rk, ri, Kuns (Where Kusn is unsigned)
Likewise DLX has a subui rk, ri, Kusn. (Mips does not)
Thus they should be:
def ADDui : ArithI<0x09, "addui", add,...
2010 Jul 06
0
[LLVMdev] Question on the use of TableGen
...:$dst, (shl:i32 CPURegs:i32:$b,
(imm:{i32:v8i16})<<P:Predicate_immZExt5>>:$c))
../../../bin/tblgen: error:
Included from .../llvm/lib/Target/MBlaze/MBlaze.td:25:
.../llvm/lib/Target/MBlaze/MBlazeInstrInfo.td:347:5: error: In BSLLI: Could
not infer all types in pattern!
def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>;
^
It seems that defining a new register class changes how the tblgen infers
the types in the DAG patterns.
So what is the right way to add a register class for a different type?
--
Regards,
Dongrui
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