Displaying 10 results from an estimated 10 matches for "arglocs".
2013 Jan 27
2
[LLVMdev] lldb cannot display structure type for llvm3.2
I find the lldb cannot display structure type information, such as "print ArgLocs.size()" as follows,
-> 593 CCValAssign &VA = ArgLocs[i];
594 EVT ValVT = VA.getValVT();
595 ISD::ArgFlagsTy Flags = Ins[i].Flags;
596 bool IsRegLoc = VA.isRegLoc();
(lldb) print ArgLocs.size()
error: call to a function 'llvm::SmallVectorTemplateCommon&l...
2013 Jan 28
0
[LLVMdev] lldb cannot display structure type for llvm3.2
This may be a debug info bug, if you could reduce it down a bit and file a
bug that'd be appreciated.
Thanks.
-eric
On Sun, Jan 27, 2013 at 12:11 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote:
> I find the lldb cannot display structure type information, such as "print
> ArgLocs.size()" as follows,
>
> -> 593 CCValAssign &VA = ArgLocs[i];
> 594 EVT ValVT = VA.getValVT();
> 595 ISD::ArgFlagsTy Flags = Ins[i].Flags;
> 596 bool IsRegLoc = VA.isRegLoc();
> (lldb) print ArgLocs.size()
> error: call to a function
>...
2019 Jul 24
2
About a new porting of GlobalIsel for RISCV
...target-specific "ValueHandler" will be created to support
calllowering.
I have made some experiment that trying to implement the "LowerReturn"
function, and it can return correctly. The code snippet may be as
follows:
...
CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
TLI.analyzeOutputArgs(MF, CCInfo, Outs, true, nullptr);
RISCVValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
RetHandler.handleArg(ArgLocs, RetInfos);
...
In order to reduce duplicated code as much as possible, and reuse part
of code from "TargetLowering&quo...
2016 Feb 01
2
TableGen customized node with mayStore attribute is deleted if there is no use
...dst, $src",
[(set i32:$dst, (MoveFlag i32:$src))]>;
For example, I add this node into SDAG when I want to move the formal
argument from the specific register class to other register class. I
implement it in LowerFormalArguments() like this:
....
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
VReg = RegInfo.createVirtualRegister(&FOO::BRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
SDValue Arg...
2015 Nov 25
2
need help for customized backend LowerFormalArguments
...DValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(!isVarArg && "VarArg not supported");
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_FOO);
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
const...
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...isTailCall = cast<ConstantSDNode>(Op.getOperand(3))-
>getValue() != 0;
+ SDOperand Callee = Op.getOperand(4);
+ //unsigned NumOps = (Op.getNumOperands() - 5) / 2;
+
+ // Analyze operands of the call, assigning locations to each operand.
+ SmallVector<CCValAssign, 16> ArgLocs;
+ CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
+ CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_TailCall);
+ if (isTailCall &&
+ IsEligibleForTailCallElimination(Op, DAG,CC, Callee) &&
+ PerformTailCallOpt) {
IsEligibleForTailCallElimination() should be a...
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...Node>(Op.getOperand(3))-
>> getValue() != 0;
> + SDOperand Callee = Op.getOperand(4);
> + //unsigned NumOps = (Op.getNumOperands() - 5) / 2;
> +
> + // Analyze operands of the call, assigning locations to each
> operand.
> + SmallVector<CCValAssign, 16> ArgLocs;
> + CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
> + CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_TailCall);
> + if (isTailCall &&
> + IsEligibleForTailCallElimination(Op, DAG,CC, Callee) &&
> + PerformTailCallOpt) {
>
>
> IsEligib...
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
this is definitely a bug in AA.
225 for (auto I = CS2.arg_begin(), E = CS2.arg_end(); I != E; ++I) {
226 const Value *Arg = *I;
227 if (!Arg->getType()->isPointerTy())
-> 228 continue;
229 unsigned CS2ArgIdx = std::distance(CS2.arg_begin(), I);
230 auto CS2ArgLoc = MemoryLocation::getForArgument(CS2,
CS2ArgIdx, TLI);
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
+ a few others.
After following this rabbit hole a bit, there are a lot of mutually
recursive calls, etc, that may or may not do the right thing with vectors
of pointers.
I can fix *this* particular bug with the attached patch.
However, it's mostly papering over stuff. Nothing seems to know what to do
with a memorylocation that is a vector of pointers. They all expect
memorylocation to be a