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...com/content/83cj0ebgtm998hj8 -- --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien F: (+431) 58801-18598 Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

...-- > --------------------------------------------------------------------- > Dietmar Ebner > CD Laboratory - Compilation Techniques for Embedded Processors > Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at > Technische Universitaet Wien F: (+431) 58801-18598 > Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 > 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman...

...ean. Thanks for the feedback, Jakob and Evan. Gergo -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...d Evan. > > > Gergo > -- > Gergö Barany, research assistant gergo at complang.tuwien.ac.at > Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...ocumented anywhere. This might have changed in the meantime. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,

...elector creates all necessary conversion instructions. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...here necessary. - dietmar -- --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien F: (+431) 58801-18598 Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

...l necessary conversion instructions. > > -- > Gergö Barany, research assistant > gergo at complang.tuwien.ac.at > Institute of Computer Languages > http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: > +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: > +43-1-58801-18598 > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100829/24246c54/attachment.html>

.../EPIC2/papers/s3-3-snavely.pdf --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien T: (+431) 58801-18598 Argentinierstrasse 8 / E1851 F: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

Hello list, I wonder if llvm/Clang can compile C or C++ for ARM from on x86. http://comments.gmane.org/gmane.comp.compilers.clang.devel/8896 The talk above answered 'NO' to my question, which means Clang is not yet able to cross compile for ARM on X86. Is the answer still correct for my question? I saw somewhere that Clang supports ARM on Darwin only. Then is the cross compiling

...ration. If interested, please respond directly to Andreas Krall: andi at complang.tuwien.ac.at http://www.complang.tuwien.ac.at/andi Thanks, Dietmar -- Dietmar Ebner Computer Languages Group E: ebner at complang.tuwien.ac.at Vienna University of Technology T: (+431) 58801-58521 Argentinierstrasse 8 / E1851 F: (+431) 58801-18598 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hello, is it possible to compile just an subproject? For example, just llc or lli? Cheers. Beckert. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120503/c20aa7b1/attachment.html>

Hello Everyone, Would you please send me any links to documentation on LLVM stack? I am particularly interested in knowing how each instruction in an LLVM bit code file(.ll file) affects its stack. To be specific, is it possible to map an LLVM program as operations on a stack? Thanks, Amruth

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent:

All, I apologize if this is an inappropriate question for this mailing list. If so, please recommend an appropriate place to post the question. I'm also somewhat new to LLVM, so I could have some pretty fundamental misunderstandings about what I am trying to do. I have searched for information on the llvm.org website (user's guide, programmer's manual and doxygen documentation),

...ll pointer to a valid array of the given number of elements. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...sumably) more interesting problems ;-) > > -- > Gergö Barany, research assistant > gergo at complang.tuwien.ac.at > Institute of Computer Languages > http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: > +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: > +43-1-58801-18598 > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121011/3a31c97e/attachment.html>