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...torial as reference. I have two instructions for add: add and addi (this is a pseudo instruction, but imediate operations is not available in architecture). That is my idea: When the LLVM instruction selection find addi r3 = r2 + value must convert to this: - load r1, value - add r3 = r2 + r1 In archInstrInfo.td I declared the instructions of the architecture, but I dont know how to "split" addi instruction. I tryed understand the LLVM and CPU0 documentation for solve this but I not found anything. :( Could anyone help me? Thanks Carlos -------------- next part -------------- An HTML attachm...

...t;> instruction, but imediate operations is not available in architecture). >> That is my idea: When the LLVM instruction selection find addi r3 = r2 + >> value >> >> must convert to this: >> >> - load r1, value >> - add r3 = r2 + r1 >> >> In archInstrInfo.td I declared the instructions of the architecture, but >> I dont know how to "split" addi instruction. I tryed understand the LLVM >> and CPU0 documentation for solve this but I not found anything. :( >> >> Could anyone help me? >> >> Thanks >> C...

...e is easily "fixed" (the performance is optimized) by swapping the 2nd and 3rd operands: add r1, r1, r2 # r1 <- r1 + r2 There are four banks and the formula to figure out which bank a register is in is just: r%4 Which brings me to tablegen: We've got this in our specialized ArchInstrInfo.td: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (outs info.regClass:$r1), (ins info.regClass:$r2, info....

...mmediate is a label, in machine code the immediate is a relative offset for the PC). I have spent some time looking at the PPC and SPARC backends, but obviously these are much more complicated than what I require to implement. Consequently, I am not correctly grasping the interactions between ARCHInstrInfo.td and ARCHDAGToDAGISel.cpp I did manage to hack something together based on a copy of SPARC (with a SABRE namespace etc) but the instruction selection was incorrect and I obtained a "Cannot yet select:0x..." assertion failure from SABREDAGToDAGIsel::SelectCode when I attempted a llc...