Displaying 4 results from an estimated 4 matches for "apic_io_memori".
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apic_io_memory
2009 Jun 05
1
[PATCHv3 07/13] qemu: minimal MSI/MSI-X implementation for PC
Implement MSI support in APIC. Note that MSI and MMIO APIC registers
are at the same memory location, but actually not on the global bus: MSI
is on PCI bus, APIC is connected directly to the CPU. We map them on the
global bus at the same address which happens to work because MSI
registers are reserved in APIC MMIO and vice versa.
Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
2009 Jun 05
1
[PATCHv3 07/13] qemu: minimal MSI/MSI-X implementation for PC
Implement MSI support in APIC. Note that MSI and MMIO APIC registers
are at the same memory location, but actually not on the global bus: MSI
is on PCI bus, APIC is connected directly to the CPU. We map them on the
global bus at the same address which happens to work because MSI
registers are reserved in APIC MMIO and vice versa.
Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
2009 Jun 21
0
[PATCHv2 RFC] qemu/msix: remove msix_supported safety flag
Don't add an option for platforms to disable MSI-X in all devices.
Paul Brook will find and fix all platforms that have broken MSI-X
emulation.
Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
This patch on top of my msix series v6 is a bit tongue in cheek: it
shows what can be done and Paul seems to think it's a good idea. So even
though I don't necessarily agree,
2009 Jun 21
0
[PATCHv2 RFC] qemu/msix: remove msix_supported safety flag
Don't add an option for platforms to disable MSI-X in all devices.
Paul Brook will find and fix all platforms that have broken MSI-X
emulation.
Signed-off-by: Michael S. Tsirkin <mst at redhat.com>
---
This patch on top of my msix series v6 is a bit tongue in cheek: it
shows what can be done and Paul seems to think it's a good idea. So even
though I don't necessarily agree,