search for: any_ext

...Worse, the value is spilled and the zext is not folded into the reload. > > The code I'm thinking of is in SelectionDAGISel::ComputeLiveOutVRegInfo For the testcase I'm looking at, ComputeLiveOutVRegInfo does not help because it is called prior to selection when the load is an "any_ext" load. It gets (arbitrarily) selected to LDRB, which zero-extends to 32 bits, but that's too late to affect the live-out info. MachineCSE and MachineSink do not help because the first zero-extend is folded into the load (LDRB), so the redundant zero-extend (UXTB) does not appear to be a...

Is there a way to define a register class that is storage-only? I want to have an i8 register class that I can use for loads/stores/converts, but that does not support arithmetic. It seems addOperationAction(ISD::ADD, MVT::i8, Promote) and SetPromotedToType(ISD::ADD, MVT::i8, MVT::i16) are not sufficient, as the legalizer just looks at whether or not the underlying type is legal (which it is).

On Aug 18, 2010, at 10:27 AM, Bob Wilson wrote: >> I tend to think that it isn't worth the compile time to try to microoptimize out every compare, but I could be convinced otherwise if there are important use cases we're failing to handle. I also do think that whole-function selection dags will solve a lot of grossness (e.g. much of codegen prepare) with a very clean model. >

On Aug 18, 2010, at 9:56 AM, Chris Lattner wrote: > On Aug 18, 2010, at 9:22 AM, Bob Wilson wrote: >> I'm looking at llvm-generated ARM code that has some unnecessary UXTB (zero extend) instructions, and it seems to me that doing type legalization as an entirely local transformation is not the best approach. > > That's true, but doing isel as a purely local approach

...> and the zext is not folded into the reload. > > > > The code I'm thinking of is in SelectionDAGISel::ComputeLiveOutVRegInfo > > For the testcase I'm looking at, ComputeLiveOutVRegInfo does not help > because it is called prior to selection when the load is an "any_ext" load. > It gets (arbitrarily) selected to LDRB, which zero-extends to 32 bits, but > that's too late to affect the live-out info. > > MachineCSE and MachineSink do not help because the first zero-extend is > folded into the load (LDRB), so the redundant zero-extend (UXTB)...