Displaying 11 results from an estimated 11 matches for "antisu".
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2012 Jun 12
2
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
...0<kill>, 0, pred:14, pred:%noreg; mem:Volatile ST4[%p1](tbaa=!"int")
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 2
Height : 0
Predecessors:
val SU(1): Latency=1 Reg=%R2
Successors:
antiSU(3): Latency=0
ch SU(3): Latency=0
SU(3): %R0<def> = LDRi12 %R1<kill>, 0, pred:14, pred:%noreg; mem:Volatile LD4[%p2](tbaa=!"int")
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 2
Height...
2012 Sep 20
2
[LLVMdev] Scheduling question (memory dependency)
...-------------------------------
********** List Scheduling **********
SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
# preds left : 0
# succs left : 4
# rdefs left : 0
Latency : 3
Depth : 0
Height : 0
Successors:
antiSU(2): Latency=0
antiSU(2): Latency=0
ch SU(5): Latency=0
ch SU(4294967295) *: Latency=0
SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
# preds left : 0
# succs left : 3
# rdefs left : 0
Latency : 5
Depth : 0
Height : 0...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...st Scheduling **********
> SU(0): STH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> # preds left : 0
> # succs left : 4
> # rdefs left : 0
> Latency : 3
> Depth : 0
> Height : 0
> Successors:
> antiSU(2): Latency=0
> antiSU(2): Latency=0
> ch SU(5): Latency=0
> ch SU(4294967295) *: Latency=0
>
> SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
> # preds left : 0
> # succs left : 3
> # rdefs left : 0
> Latency : 5
>...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...TH8 %X3<kill>, 162, %X1; mem:ST2[FixedStack-1]
> > # preds left : 0
> > # succs left : 4
> > # rdefs left : 0
> > Latency : 3
> > Depth : 0
> > Height : 0
> > Successors:
> > antiSU(2): Latency=0
> > antiSU(2): Latency=0
> > ch SU(5): Latency=0
> > ch SU(4294967295) *: Latency=0
> >
> > SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
> > # preds left : 0
> > # succs left : 3
> > # rdefs left...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...ds left : 0
> > > > # succs left : 4
> > > > # rdefs left : 0
> > > > Latency : 3
> > > > Depth : 0
> > > > Height : 0
> > > > Successors:
> > > > antiSU(2): Latency=0
> > > > antiSU(2): Latency=0
> > > > ch SU(5): Latency=0
> > > > ch SU(4294967295) *: Latency=0
> > > >
> > > > SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
> > > > # preds left : 0
>...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...ixedStack-1]
> > > # preds left : 0
> > > # succs left : 4
> > > # rdefs left : 0
> > > Latency : 3
> > > Depth : 0
> > > Height : 0
> > > Successors:
> > > antiSU(2): Latency=0
> > > antiSU(2): Latency=0
> > > ch SU(5): Latency=0
> > > ch SU(4294967295) *: Latency=0
> > >
> > > SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
> > > # preds left : 0
> > > # succs left...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...t; > # succs left : 4
> > > > > # rdefs left : 0
> > > > > Latency : 3
> > > > > Depth : 0
> > > > > Height : 0
> > > > > Successors:
> > > > > antiSU(2): Latency=0
> > > > > antiSU(2): Latency=0
> > > > > ch SU(5): Latency=0
> > > > > ch SU(4294967295) *: Latency=0
> > > > >
> > > > > SU(1): %R5<def> = LHA 162, %X1; mem:LD2[%0]
> > > > >...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...t;def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
# preds left : 0
# succs left : 3
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(3): Latency=1
val SU(2): Latency=1
antiSU(2): Latency=0
SU(2): %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
# preds left : 2
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(1): Latency=1 Reg=%vreg10
antiSU(1...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
On Jun 12, 2012, at 10:22 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> Hello everyone,
>
> I am working on a release based on the branch 3.1 version of code.
> Unfortunately it has enough differences that exact rev does not apply.
> I am hitting an assert in liveness update with seemingly trivial code
> (attached).
>
>
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
Hello everyone,
I am working on a release based on the branch 3.1 version of code.
Unfortunately it has enough differences that exact rev does not apply.
I am hitting an assert in liveness update with seemingly trivial code
(attached).
/local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter
valAnalysis.cpp:1078: void
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
....0.in]
> IntRegs:%vreg10,%vreg9
> # preds left : 0
> # succs left : 3
> # rdefs left : 1
> Latency : 1
> Depth : 0
> Height : 0
> Successors:
> val SU(3): Latency=1
> val SU(2): Latency=1
> antiSU(2): Latency=0
>
> SU(2): %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> # preds left : 2
> # succs left : 0
> # rdefs left : 1
> Latency : 1
> Depth : 0
> Height : 0
> Predecessors:
&g...