search for: antidep

...ing phase ordering problem, but of course it's more complex to implement and modularize. (I'm unsure if it's possible to exploit the current register allocator code easily with it). Another solution (which we use in TCE) is to use register renaming. That is, rename schedule-restricting antideps introduced by the pre-RA "on the fly" during scheduling. It's sort of a middle ground solution that allows modularizing the proper RA to a separate pass cleanly. However, its proper implementation goes step-by-step towards the integrated allocator (smarter the renamer becomes, more i...

...m, but of course it's more > complex to implement and modularize. (I'm unsure if it's possible to > exploit the current register allocator code easily with it). > > Another solution (which we use in TCE) is to use register renaming. > That is, rename schedule-restricting antideps introduced by the pre-RA > "on the fly" during scheduling. It's sort of a middle ground solution > that allows modularizing the proper RA to a separate pass cleanly. > However, its proper implementation goes step-by-step towards the > integrated allocator (smarter the ren...

Ivan, IMHO the current bundle infrastructure is in need of some additional features - not only bundle handling utilities, but also support for liveness computation, several (key) code transformation passes etc. (see my recent post for conditional defs for instance). Does your back-end perform any substantial transformations to the code _after_ the second pass (postRA) scheduler and bundle

...39;struct-path-tbaa' defined more than once! <premain>: CommandLine Error: Argument 'enable-tbaa' defined more than once! <premain>: CommandLine Error: Argument 'enable-bc-uselist-preserve' defined more than once! <premain>: CommandLine Error: Argument 'agg-antidep-debugmod' defined more than once! --------------- end snip, but this continues and continues! ------------------- The "Result = 55" is the correct return value from compiling the first source file (i.e fib(10)). Processing the second causes the repeating <premain> complaints....

Hi, I'm working on a custom top-down post RA scheduler which builds bundles at the same time for our VLIW processor. I've borrowed most of the implementation from the resource priority queue implemented for the existent VLIW scheduler but applied to the context of MI scheduling. Basically, instructions that are likely to be bundled must be scheduled first (i.e. get higher priority).