Displaying 4 results from an estimated 4 matches for "anl_0_7".
2012 Jan 19
4
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...cases where cross class joins are carried out that makes
the code turn out illegal, because the "new" register class is not
allowed in all instructions where it is now used.
For example, by joining %vreg4, %vreg7 and %vreg9 the following code
%vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
%vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
%vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
is turned into
%vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
aN32_0_7:%vreg4
The load instruction how...
2012 Jan 19
0
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...s are carried out that makes
> the code turn out illegal, because the "new" register class is not
> allowed in all instructions where it is now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:...
2012 Jan 20
1
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...s are carried out that makes
> the code turn out illegal, because the "new" register class is not
> allowed in all instructions where it is now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:...
2012 Jan 05
0
[LLVMdev] Spilling of partly (un)defined registers
...# *** IR Dump Before Linear Scan Register Allocator ***:
# Machine code for function accumconv:
Function Live Ins: %a0_gh in %vreg0, %a1_gh in %vreg1
BB#0: derived from LLVM BB %0
Live Ins: %a0_gh %a1_gh
%vreg1<def> = COPY %a1_gh; aNgh_0_7:%vreg1
[...]
%vreg56<def> = mv_any16 0; aNl_0_7:%vreg56
%vreg57<def> = REG_SEQUENCE %vreg1, hi24, %vreg56, lo16;
aN40_0_7:%vreg57 aNgh_0_7:%vreg1 aNl_0_7:%vreg56
So the in-argument in a1_gh is saved in vreg1, and used later in a
REG_SEQUENCE instruction to write a full register, vreg57.
After the REG_SEQUENCE has been eliminated we inst...