search for: andrr

...ef>, $1:[reguse:GPR], %R4, <!3> %R0<def> = ANDri %R7, 1, pred:14, pred:%noreg, opt:%CPSR<def> %R0<def> = MOVr %LR, pred:1, pred:%CPSR<kill>, opt:%noreg %R1<def> = EORrr %R0, %LR, pred:14, pred:%noreg, opt:%noreg %R1<def> = ANDrr %R9, %R1<kill>, pred:14, pred:%noreg, opt:%noreg %R2<def> = ADDrr %R8, %R2<kill>, pred:14, pred:%noreg, opt:%CPSR<def> %R3<def> = ADCrr %R9, %R3<kill>, pred:14, pred:%noreg, opt:%noreg, %CPSR<imp-use,kill> %R0<def> = ANDrr %R3&...

...MBBs: BB#315: derived from LLVM BB %bb Predecessors according to CFG: BB#314 %reg1731<def> = SETHIi 1856 %reg1732<def> = ORri %G0, 1 %reg1733<def> = SLLrr %reg1732, %reg1729 %reg1734<def> = ORri %reg1731, 1 %reg1735<def> = ANDrr %reg1733, %reg1734 %reg1736<def> = SUBCCri %reg1735, 0, %ICC<imp-def> BCOND <BB#3>, 9, %ICC<imp-use> BA <BB#53> Successors according to CFG: BB#3 BB#53 BB#3: derived from LLVM BB %bb1 Predecessors according to CFG: BB#315 %reg17...

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty

...ruction. // ===---------------------------------------------------------------------===// // Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types. // def : InstRW< [WriteALU], (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr", "BICrr")>; This same instruction is defined in the ARMInstrInfo.td as inheriting from AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU, ReadALU]> with the instruction. defm AND : AsI1_bin_irs&...

...ns: %L1 %L0 %L3 %L2 %L4 > Predecessors according to CFG: BB#6 > %L5<def> = SETHIi 1856 > %L6<def> = ORri %G0, 1 > %L3<def> = SLLrr %L6<kill>, %L3<kill> > %L5<def> = ORri %L5<kill>, 1 > %L3<def> = ANDrr %L3<kill>, %L5<kill> > %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> > BCOND <BB#8>, 9, %ICC<imp-use,kill> > NOP > BA <BB#68> > NOP > > which leads MachineBasicBlock::isOnlyReachableByFallt...

...2 %L4 >> Predecessors according to CFG: BB#6 >> %L5<def> = SETHIi 1856 >> %L6<def> = ORri %G0, 1 >> %L3<def> = SLLrr %L6<kill>, %L3<kill> >> %L5<def> = ORri %L5<kill>, 1 >> %L3<def> = ANDrr %L3<kill>, %L5<kill> >> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> >> BCOND <BB#8>, 9, %ICC<imp-use,kill> >> NOP >> BA <BB#68> >> NOP >> >> which leads MachineBasicBlock...

...decessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<def> = ANDrr %R3<kill>, %R6<kill>, pred:14, pred:%noreg, opt:%noreg > %R6<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg > TSTri %R3<kill>, 255, pred:14, pred:%noreg, %CPSR<imp-def>; > Bcc <BB#9>, pred:0, pred:%CPSR<kill>; > > BB#8: > Live Ins: %LR...

I'm writing a back-end for a target in which all dyadic instructions support one register and one memory operand but only some instructions support two register operations. For example ADDrm and ADDrr are supported, ANDrm is supported but ANDrr isn't. I've written descriptions for ADDrm, ADDrr and ANDrm in my InstrInfo.td file but instruction selection fails when presented with an AND that has two register operands, e.g. e = (a + b) & (c + d); I guess I need to force one of the operands of the AND operator into a stack slot...

...decessors according to CFG: BB#6 >>> %L5<def> = SETHIi 1856 >>> %L6<def> = ORri %G0, 1 >>> %L3<def> = SLLrr %L6<kill>, %L3<kill> >>> %L5<def> = ORri %L5<kill>, 1 >>> %L3<def> = ANDrr %L3<kill>, %L5<kill> >>> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> >>> BCOND <BB#8>, 9, %ICC<imp-use,kill> >>> NOP >>> BA <BB#68> >>> NOP >>> >>> wh...

...ding to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; > mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<def> = ANDrr %R3<kill>, %R6<kill>, pred:14, pred:%noreg, opt:%noreg > %R6<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg > TSTri %R3<kill>, 255, pred:14, pred:%noreg, %CPSR<imp-def>; > Bcc <BB#9>, pred:0, pred:%CPSR<kill>; > > > BB#8: >...