Displaying 6 results from an estimated 6 matches for "andn32rr".
2013 Mar 21
9
[LLVMdev] Simpler types in TableGen isel patterns
Currently, instruction selection patterns are defined like this:
def : Pat<(and (not GR32:$src1), GR32:$src2),
(ANDN32rr GR32:$src1, GR32:$src2)>;
def : Pat<(and (not GR64:$src1), GR64:$src2),
(ANDN64rr GR64:$src1, GR64:$src2)>;
TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the register classes in a pattern like that. Selecti...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
...uiuc.edu, llvmdev at cs.uiuc.edu
> Sent: Thursday, March 21, 2013 1:26:25 PM
> Subject: [LLVMdev] Simpler types in TableGen isel patterns
>
> Currently, instruction selection patterns are defined like this:
>
> def : Pat<(and (not GR32:$src1), GR32:$src2),
> (ANDN32rr GR32:$src1, GR32:$src2)>;
> def : Pat<(and (not GR64:$src1), GR64:$src2),
> (ANDN64rr GR64:$src1, GR64:$src2)>;
>
> TableGen infers the types of $src1 and $src2 from the specified
> register classes, and that is the only purpose of the register
> classes i...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
Hey Jakob,
On Thu, Mar 21, 2013 at 2:26 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
> Currently, instruction selection patterns are defined like this:
>
> def : Pat<(and (not GR32:$src1), GR32:$src2),
> (ANDN32rr GR32:$src1, GR32:$src2)>;
> def : Pat<(and (not GR64:$src1), GR64:$src2),
> (ANDN64rr GR64:$src1, GR64:$src2)>;
>
> TableGen infers the types of $src1 and $src2 from the specified register
> classes, and that is the only purpose of the register classes in a pat...
2013 Mar 21
1
[LLVMdev] Simpler types in TableGen isel patterns
...> > Sent: Thursday, March 21, 2013 1:26:25 PM
> > Subject: [LLVMdev] Simpler types in TableGen isel patterns
> >
> > Currently, instruction selection patterns are defined like this:
> >
> > def : Pat<(and (not GR32:$src1), GR32:$src2),
> > (ANDN32rr GR32:$src1, GR32:$src2)>;
> > def : Pat<(and (not GR64:$src1), GR64:$src2),
> > (ANDN64rr GR64:$src1, GR64:$src2)>;
> >
> > TableGen infers the types of $src1 and $src2 from the specified
> > register classes, and that is the only purpose of the...
2013 Mar 23
0
[LLVMdev] Simpler types in TableGen isel patterns
On Thu, Mar 21, 2013 at 2:26 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
> Currently, instruction selection patterns are defined like this:
>
> def : Pat<(and (not GR32:$src1), GR32:$src2),
> (ANDN32rr GR32:$src1, GR32:$src2)>;
> def : Pat<(and (not GR64:$src1), GR64:$src2),
> (ANDN64rr GR64:$src1, GR64:$src2)>;
>
> TableGen infers the types of $src1 and $src2 from the specified register
> classes, and that is the only purpose of the register classes in a pat...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
On Mar 21, 2013, at 11:26 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> I think in most cases it would be much simpler and safer to specify pattern types directly:
>
> def : Pat<(and (not i32:$src1), i32:$src2),
> (ANDN32rr i32:$src1, i32:$src2)>;
> def : Pat<(and (not i64:$src1), i64:$src2),
> (ANDN64rr i64:$src1, i64:$src2)>;
>
> This doesn't lose any type checking because the register classes of the instructions in the output pattern are still checked. It avoids the problem w...