search for: anded

I''m already successfully testing before_filters in application_controller courtesy of this blog post: http://www.movesonrails.com/articles/2008/01/23/spec-ing-your-application-controller However, i can;''t work out how to test the sort of method that is added to application_controller so that all controllers can use it. It must be something simple that i''m doing

Hello! I noticed that in some cases clang generates sequence of AND+TST instructions: For example: AND x3, x2, x1 TST x2, x1 I think these instructions should be merged to one: ANDS x3, x2, x1 ( because TST <Xn>, <Xm> is alias for ANDS XZR, <Xn>, <Xm> -

Hey guys, I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. In the IR, we represent a 4b vector mask as <4 x i1>. This assumes that the storage container for this type is also 4b, but it's not. The smallest mask register on SKX is 8b. This also implies that the smallest load/store moves 8b. We run into problems when we try to optimize ANDs (full test case

Ok, thank you, I will implement it then. As far as I see this optimization should be done in AArch64LoadStoreOptimizer, is it right? From: Eli Friedman [mailto:efriedma at quicinc.com] Sent: Thursday, November 21, 2019 11:55 PM To: Kosov Pavel <kosov.pavel at huawei.com>; LLVM Dev <llvm-dev at lists.llvm.org> Subject: RE: [llvm-dev] [ARM] Peephole optimization ( instructions tst +

On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> On Oct 20, 2016, at 8:54 AM, Cameron McInally via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hey guys, >> >> I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. >> >> In the IR, we represent a 4b vector mask as <4 x i1>.

Thank you for the help. The relocation type value is anded with 0xffffffffL. (RuntimeDyldMachO.cpp:214) Maybe this mask should be different? Anyway, it seems like this relocation isn't implemented. (RuntimeDyldMachO.cpp:104) From: Jiong Wang <jiwang at tilera.com<mailto:jiwang at tilera.com>> Date: Tue, 9 Apr 2013 09:42:03 -0400 To: Eran W...

Hello, I found out an unexpected behaviour of search queries with mixed "AND" and "OR". With search query "\( condA OR condB condC \)" I get an error: Fatal: Use parenthesis when mixing ANDs and ORs if I switch left and right OR-part and use the query "\( condB condC OR condA \)" I get a result, but it is not the expected result of the query "\(

Hi, When we meet UEFI or EFI firmware, lots of linux os release use GRUB bootloader. But I wanna use isolinux to boot the installation environment and also the linux os installed. Some question puzzled me. Now, I look for your help: 1. I didn't found information about how to use syslinux(isolinux,etc.) in uefi. I wanna know that are there some differences of the isolinux configuration

Having just discovered "Task Views" I see there isn't one for ecology/environmental science. I don't have the expertise to help with this, but I think it would be a very useful addition if there was any person (s) on the list willing to help create such a Task View. I am sure the maintainers of the Task Views will pick up on any responses to this post from volunteers. I

On 10/20/2016 9:28 AM, Cameron McInally via llvm-dev wrote: > I should have attached the generated asm to save some trouble. > Apologies for that and attaching now... > > > > On Thu, Oct 20, 2016 at 12:26 PM, Cameron McInally > <cameron.mcinally at nyu.edu> wrote: >> On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote:

...ry format, but the hex value of 218103811 is 0xd000003 (maybe the relocation type is RIT_Generic_PreboundLazyPointer = 3), something looks like a relocation entry composed of "symbol index" + "relocation type". maybe something is wrong, that the relocation entry is not anded with a mask to get the final relocation type. --- Regards, Jiong > Did someone encounter a similar error? Or can direct me to changes > that I need to do while migrating from JIT to MCJIT? > > Thanks. > > > _______________________________________________ > LLVM Developer...

...p? -Andy From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Weiss, Eran Sent: Tuesday, April 09, 2013 11:51 PM To: Jiong Wang Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Migration from JIT to MCJIT Thank you for the help. The relocation type value is anded with 0xffffffffL. (RuntimeDyldMachO.cpp:214) Maybe this mask should be different? Anyway, it seems like this relocation isn't implemented. (RuntimeDyldMachO.cpp:104) From: Jiong Wang <jiwang at tilera.com<mailto:jiwang at tilera.com>> Date: Tue, 9 Apr 2013 09:42:03 -0400 To: Eran W...

Hi All, Been having a problem constructing a suitable pattern to represent some vector operations in the DAG. Stuff like andx/orx operations where elements of a vector are anded/ored together. My approach thus far has been to extract the sub elements of the vector and and/or those elements. This is ok for 4 vectors of i32s, but becomes cumbersome for v16i8s. Example instruction: andx $dst $v1 Pattern: [(set RC:$dst, (and (i32 (vector_extract(vt VC:$src), 0 ) ),...

Hi, I'm migrating my code (running on mac) from using JIT to MCJIT. My code generates in memory, mostly using the llvm-c api, and then runs the generated code. When I try to use MCJIT I encounter a problem with relocations of external symbols – functions compiled statically beforehand with gcc. I get the following error: Invalid relocation type! UNREACHABLE executed at

...c.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Weiss, Eran > Sent: Tuesday, April 09, 2013 11:51 PM > To: Jiong Wang > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Migration from JIT to MCJIT > > Thank you for the help. > > The relocation type value is anded with 0xffffffffL. (RuntimeDyldMachO.cpp:214) > Maybe this mask should be different? > Anyway, it seems like this relocation isn't implemented. (RuntimeDyldMachO.cpp:104) > > From: Jiong Wang <jiwang at tilera.com> > Date: Tue, 9 Apr 2013 09:42:03 -0400 > To: Eran Weiss...

qemu recently added support for 3dnow instructions. Because of that, 3dnow will be featured among cpuid bits. But this will break kvm in cpus that don't have those instructions (which includes my laptop). So we fixup our cpuid before exposing it to the guest. Signed-off-by: Glauber Costa <gcosta at redhat.com> --- arch/x86/kvm/x86.c | 22 ++++++++++++++++++----

qemu recently added support for 3dnow instructions. Because of that, 3dnow will be featured among cpuid bits. But this will break kvm in cpus that don't have those instructions (which includes my laptop). So we fixup our cpuid before exposing it to the guest. Signed-off-by: Glauber Costa <gcosta at redhat.com> --- arch/x86/kvm/x86.c | 22 ++++++++++++++++++----

This seems disappointing. Casting any value to an integral type should yield a value within the range of that integral type. The value can be anything, but it should be within range. i.e. it should be as if I anded it with (type)~(type)0. i.e. int i = (signed char)x; assert(i >= -128 && i <= 127); int i = (unsigned char)x; assert(i >= 0 && i <= 255); seem very reasonable, assuming there is no "trap" before the assert. - Jay ________________________________ Fr...

Hi all, Is it planned to add support of rotations to IR? Thanks, Aleksey Zasenko -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151119/c897b935/attachment.html>

Putting together a system build, AMD based. Ryzen 5 CPU on X570 chipset with Radeon RX480 GPU. Guessing this will be supported by Centos OK? (Unless you know different! :-) ) https://www.amd.com/en/support/graphics/radeon-400-series/radeon-rx-400-series/radeon-rx-480 Shows driver support. Does Centos repo's hold these drivers or do I download after the install please? TiA -- Dave