Displaying 3 results from an estimated 3 matches for "and_i32".
2011 Sep 13
3
[LLVMdev] Setting priority in instruction selection
...ot;mov $dst, $src",
[(set GPRI32:$dst, imm:$val)]>;
Now, what is happening with this code, (A & B) | (C & ~B), where B is an immedate and ~B is an inverse of it,
instead of getting
LOADCONST_i32 r0 B
BFI_i32 r1, A, C, r0
I am getting
LOADCONST_i32 r0, B
LOADCONST_i32 r1, ~B
AND_i32 r2, A, r0
AND_i32 r3, C, r1
OR_i32 r4, r2, r3
because the LOADCONST is getting matched before the bfi_pat1 pattern fragment.
I know I can write C++ code that will generate a pattern fragment and handle this issue, but I don't want to duplicate behavior if it already exists.
Any ideas?
Thanks...
2011 Sep 13
0
[LLVMdev] Setting priority in instruction selection
...hat is happening with this code, (A & B) | (C & ~B), where B is an
> immedate and ~B is an inverse of it,
>
> instead of getting
>
> LOADCONST_i32 r0 B
>
> BFI_i32 r1, A, C, r0
>
> I am getting
>
> LOADCONST_i32 r0, B
>
> LOADCONST_i32 r1, ~B
>
> AND_i32 r2, A, r0
>
> AND_i32 r3, C, r1
>
> OR_i32 r4, r2, r3
>
> because the LOADCONST is getting matched before the bfi_pat1 pattern
> fragment.
>
>
>
> I know I can write C++ code that will generate a pattern fragment and handle
> this issue, but I don't want to d...
2011 Sep 13
1
[LLVMdev] Setting priority in instruction selection
...> > immedate and ~B is an inverse of it,
> >
> > instead of getting
> >
> > LOADCONST_i32 r0 B
> >
> > BFI_i32 r1, A, C, r0
> >
> > I am getting
> >
> > LOADCONST_i32 r0, B
> >
> > LOADCONST_i32 r1, ~B
> >
> > AND_i32 r2, A, r0
> >
> > AND_i32 r3, C, r1
> >
> > OR_i32 r4, r2, r3
> >
> > because the LOADCONST is getting matched before the bfi_pat1 pattern
> > fragment.
> >
> >
> >
> > I know I can write C++ code that will generate a pattern fragmen...