Displaying 6 results from an estimated 6 matches for "and5".
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2018 May 15
0
Rotates, once again
...an estimated cost of 1 for instruction: %and = and i32
%cond, 31
Cost Model: Found an estimated cost of 1 for instruction: %shl = shl i32
%1, %and
Cost Model: Found an estimated cost of 1 for instruction: %sub = sub nsw
i32 0, %cond
Cost Model: Found an estimated cost of 1 for instruction: %and5 = and i32
%sub, 31
Cost Model: Found an estimated cost of 1 for instruction: %shr = lshr i32
%1, %and5
Cost Model: Found an estimated cost of 1 for instruction: %or = or i32
%shl, %shr
The broken cost model also affects unrolling and inlining. Size costs are
overestimated for a target that has...
2016 Jul 27
2
Remove zext-unfolding from InstCombine
...t i8 @goo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
entry:
%conv = sext i8 %a to i32
%and = and i32 %conv, 1
%cmp = icmp ne i32 %and, 0
%conv1 = zext i1 %cmp to i32
%conv2 = sext i8 %b to i32
%cmp3 = icmp ne i32 %conv2, 0
%conv4 = zext i1 %cmp3 to i32
%and5 = and i32 %conv1, %conv4
%tobool = icmp ne i32 %and5, 0
%lnot = xor i1 %tobool, true
%lnot.ext = zext i1 %lnot to i32
%conv6 = trunc i32 %lnot.ext to i8
ret i8 %conv6
}
```
For both functions, the `icmp` operations will be immediately followed by `zext` instructions, which will directly...
2018 May 14
5
Rotates, once again
Hi everyone!
I recently ran into some interesting issues with generation of rotate instructions - the details are in the bug tracker (https://bugs.llvm.org/show_bug.cgi?id=37387 and related bugs) for those interested - and it brought up the issue of rotates in the IR again. Now this is a proposal that has been made (and been rejected) several times, but I've been told that this time round we
2016 Aug 04
2
Remove zext-unfolding from InstCombine
...8 signext %b) local_unnamed_addr #0 {
> entry:
> %conv = sext i8 %a to i32
> %and = and i32 %conv, 1
> %cmp = icmp ne i32 %and, 0
> %conv1 = zext i1 %cmp to i32
> %conv2 = sext i8 %b to i32
> %cmp3 = icmp ne i32 %conv2, 0
> %conv4 = zext i1 %cmp3 to i32
> %and5 = and i32 %conv1, %conv4
> %tobool = icmp ne i32 %and5, 0
> %lnot = xor i1 %tobool, true
> %lnot.ext = zext i1 %lnot to i32
> %conv6 = trunc i32 %lnot.ext to i8
> ret i8 %conv6
> }
> ```
>
> For both functions, the `icmp` operations will be immediately followed...
2016 Jul 21
2
Remove zext-unfolding from InstCombine
Hi all,
I have a question regarding a transformation that is carried out in InstCombine, which has been introduced by r48715. It unfolds expressions of the form `zext(or(icmp, (icmp)))` to `or(zext(icmp), zext(icmp)))` to expose pairs of `zext(icmp)`. In a subsequent iteration these `zext(icmp)` pairs could then (possibly) be optimized by another optimization (which has already been there before
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...c.ptr = getelementptr inbounds i16* %b, i32 1
%.lobit = ashr i16 %0, 15
store i16 %.lobit, i16* %b, align 2
%incdec.ptr2 = getelementptr inbounds i16* %a, i32 8
%1 = load i16* %add.ptr, align 2, !tbaa !5
%incdec.ptr3 = getelementptr inbounds i16* %b, i32 2
%conv4 = zext i16 %1 to i32
%and5 = and i32 %conv4, 32767
%conv6 = trunc i32 %and5 to i16
store i16 %conv6, i16* %incdec.ptr, align 2, !tbaa !5
%cmp = icmp eq i32 %and5, 32767
br i1 %cmp, label %if.then11, label %if.end28
if.then11: ; preds = %entry
%call = tail call fastcc i32 @eis...