search for: anchient

...for each table reference based on what computaions go there. One of the ia32 is grand for writing to*, but cant be used to move mem to reg. Obviously this is an intentional design. Optimizer should handle this based on machine type and a model of hardware capabilities. (again back to HDL and the anchient ISDL specs for modeling.. but avoiding the new uml except at higher layers) so. a table that resolves to various data blocks, set the base pointers accordingly, then process. morphic code and code coppied to a new cs for runtime (load to chip) can have its own buffers, stacks are idiotic. (this...

Hi, I am having a lot of trouble with getting 0s2 to talk with samba. They seem to be making the right noises at handshake time, and seem to set up a session no problems (using ethereal, monitoring packets). However, when it comes to actually transferring information (such as doing a listing of a share from the os2 box) it crashes with the error: Open AndX Request, Path: \OSO001.MSG; Read

I realize I am one of the few who uses the segment registers (especially CS and DS) on the ia32 chips for example, and a definite few with complete segregation models that rival specialized physical processors... GCC still fails to use these correctly and if your LLVM still depends on either Generic or some of the RTL models they use in various processor definitions, I express concern for