search for: amilkanthwar

...read old .bc but NOT old .ll files) Supporting latter is more useful, IMO, because then I wouldn't have to modify all my sources. And who are "we" here? On Fri, Aug 12, 2016 at 7:21 PM, Tim Northover <t.p.northover at gmail.com> wrote: > On 12 August 2016 at 06:42, Madhur Amilkanthwar via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Ideally, I would expect backward compatibility from LLVM tools; and not > > requiring to modify the code again. > > > > What is LLVM's philosophy here? > > We support backwards compatibility (i.e. newe...

...ly. Is there any way to dump the numerical representation of input textual LLVM IR on terminal? "-f" option to llvm-as did not help. -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160819/e016c56c/attachment.html>

Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org>於 2020年8月9日 週日，上午1:53寫道： > Hi Paul, > I hope you have gone through > https://llvm.org/docs/Contributing.html#how-to-submit-a-patch. > > Generally, I would do 'git add' on the new file. 'git diff' should show me > the...

...ll.com> wrote: > Your reply suggests that there is a way to see debug messages from > TableGen. Is that what you meant? If so, can you explain how that works? > (Sorry, I should know the answer to this question, but I'm quite the > newbie.) > > At 8/5/2020 04:15 AM, Madhur Amilkanthwar wrote: > >Hi Paul, > >If all you care about is debugging then for now we can just emit a few > more debug messages which would help to "trace" the flow. To distinguish > traces you can prefix it with some known string. I don't think you really > need a 'trace&...

...SA graphs? I have a complicated loop and I need to do some analysis around it. Can anyone please point me to source of identification part? -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161016/783ff3ed/attachment.html>

Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (which part of the code you don't understand). > > On Thu, Jul 6, 2017 at 9:53 AM, Raghavan, Venugopal via llvm-dev <llvm-dev a...

...y PTX code automatically or by directives without involvement of CUDA. This way, I am talking about avoiding source to source compiler approach where c code is converted automatically into CUDA, instead I am saying directly to convert C code to PTX assembly. On Tue, Dec 11, 2018 at 12:19 PM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > You can skip CUDA code generation and target PTX assembly. PTX is a common > assembly language for NVIDIA's GPU. You may want to look at PPCG, Pluto > projects to get a hint of how automatic CUDA code can be generated by > compilers. They a...

...lly, I would expect backward compatibility from LLVM tools; and not requiring to modify the code again. What is LLVM's philosophy here? -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160812/7ca4f96a/attachment.html>

...if you called it you would not get a solution from it, right? Thanks. Regards, Venugopal Raghavan From: qcolombet at apple.com [mailto:qcolombet at apple.com] Sent: Friday, July 07, 2017 2:16 AM To: Raghavan, Venugopal <Venugopal.Raghavan at amd.com> Cc: llvm-dev at lists.llvm.org; Madhur Amilkanthwar <madhur13490 at gmail.com> Subject: Re: [llvm-dev] LLVM's loop strength reduction module Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org<mailt...

I am ready to submit my first real submission for review with Phabricator. Please forgive my meager knowledge of Git. I did a 'git diff' to generate the diff file. The contents look good. However, there is one new file, a TableGen test file. How do I get that file included in the diff, or otherwise included in the submission?

On Tue, Oct 13, 2020 at 10:47 AM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > What do you guys think about the below enhancements? > > 5. !getdagrestype(dag [, index]) - Returns type of result value. If the DAG computes multiple values then return type of 'index'th result. > > 6. !setdagrestype(dag target_dag,...

Hi, My name is Venugopal Raghavan and I work in AMD. I was trying to understand the code in the file LoopStrengthReduce.cpp but I am making very slow progress. Is there any additional documentation available that would help me understand the code, like a PPT presentation or a design document or maybe a paper? I did not find anything on the Internet. There are comments interspersed in the code

> On Apr 11, 2017, at 10:25 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am interested in knowing more. > 1. What benchmarks does LLVM community use for compile-time study? I see CTMark, but is that the only one being analyzed? CTMark is not cast in stone. Its purpose is for the community to have a...

...________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200805/92cb8870/attachment.html>

Adding -debug to a -gen-dag-isel run can also print useful information about the parsed patterns. On Wed, Jul 15, 2020 at 10:44 AM Matt Arsenault via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > > On Jul 15, 2020, at 13:33, Rotate Right via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Is there a backend to Tablegen which can dump a map of

...at these are the troubles, I'm just saying that it has some features and we have some problems to be solved. But lack of labels, label arithmetics in DWARF sections is the real problem, because LLVM actively uses it in DWARF sections Best regards, Alexey Bataev 8 нояб. 2017 г., в 5:35, Madhur Amilkanthwar <madhur13490 at gmail.com<mailto:madhur13490 at gmail.com>> написал(а): I don't understand the use case and reasons to blame PTXAS compiler here. >>a) Supports DWARF-2 only. What would you like to achieve with DWARF-3+ that you cannot do with DWARF2? >> b) Labels are...

I understood that the name is a matching tag for the operand and not its name (as in named macro or function arguments). However, I was assuming that the names in any one DAG node had to be unique and so could serve as selectors for operands. But a quick investigation shows that I was wrong: names can be duplicated in the same node. So DAG indexes are integers only. At 10/12/2020 01:46 PM,

@Ees, Oh, I see what you mean now. Doing such analysis would be useful for a thread block and not just a single thread but as you say you are onto something bigger than just a thread. We had published a short paper in ICS around this which uses polyhedral techniques to do such analysis and reason about uncoalesced access patterns in Cuda programs. You can find paper at

Hi, I needed to debug some CUDA code in my project; however, although I used -g when compiling the source code, no source-level information is available in cuda-gdb or cuda-memcheck. Specifically, below is what I did: 1) For a CUDA file a.cu, generate IR files: clang++ -g -emit-llvm --cuda-gpu-arch=sm_35 -c a.cu; 2) Instrument the device code a-cuda-nvptx64-nvidia-cuda-sm_35.bc (generated

Hi all, As part of my research I want to investigate the relation between the grid's geometry and the memory accesses of a kernel in common gpu benchmarks (e.g Rodinia, Polybench etc). As a first step i want to answer the following question: - Given a kernel function with M possible memory accesses. For how many of those M accesses we can statically infer its location given concrete values