Displaying 5 results from an estimated 5 matches for "amdgpuusage".
2019 Dec 17
2
llvm/docs/AMDGPUUsage.rst ERROR: Malformed table
...oject/build/docs/html"
/home/lsandov1/.local/lib/python2.7/site-packages/recommonmark/parser.py:75:
UserWarning: Container node skipped: type=document
warn("Container node skipped: type={0}".format(mdnode.t))
Warning, treated as error:
/home/lsandov1/repos/llvm-project/llvm/docs/AMDGPUUsage.rst:1317: ERROR:
Malformed table.
Column span alignment problem in table line 10.
================= ============== ========= ================================
String Key Value Type Required? Description
================= ============== ========= ================================
"Na...
2017 Dec 05
3
[AMDGPU] Strange results with different address spaces
...224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
Which is produced by the IR in as0.ll
The only difference in the two IR dumps is that the parameters to the kernel are in different address spaces. https://llvm.org/docs/AMDGPUUsage.html#amdgpu-opencl states that address space 1 should be the global address space for amdgiz runtimes like ROCm and AS 0 is the generic (flat) address space. Is this working as intended and do I something wrong with the address spaces for AMDGPU or is this some undesired behavior and a possible bug...
2020 Jul 26
2
[LAA] RtCheck on pointers of different address spaces.
...f 4 different memory operations referring two global objects of different address spaces.
One from global constant (address space 4, addr_size = 64) and the other from local, LDS (address space 3, addr_size= 32).
(Details of various address spaces available for AMDGPU backend: https://llvm.org/docs/AMDGPUUsage.html#address-spaces)
With upstream compiler, the testcase fails with a crash (given at the end of the e-mail) in the opt while trying to generate the RT check for these pointers. Precisely, with two pointers of different address spaces.
The operand type check fails while trying to insert a 'Ad...
2020 Jul 26
2
[LAA] RtCheck on pointers of different address spaces.
...f 4 different memory operations referring two global objects of different address spaces.
One from global constant (address space 4, addr_size = 64) and the other from local, LDS (address space 3, addr_size= 32).
(Details of various address spaces available for AMDGPU backend: https://llvm.org/docs/AMDGPUUsage.html#address-spaces<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fllvm.org%2Fdocs%2FAMDGPUUsage.html%23address-spaces&data=02%7C01%7CChristudasan.Devadasan%40amd.com%7C4a42db7316004baa429c08d83160f7e7%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637313639833494292&sda...
2018 Sep 05
4
Can I control HSA config generated by AMDGPU backend?
...ch_ptr = 1" so that
> it's compatible with clrxasm.
>
>
>
> Thanks,
>
> Changdao
>
>
>
> On Mon, Sep 3, 2018 at 5:25 AM Tamazov, Artem <Artem.Tamazov at amd.com>
> wrote:
>
> Hello,
>
>
>
> Please look into https://llvm.org/docs/AMDGPUUsage.html.
>
>
>
> > My target is amdgpu--amdhsa.
>
>
>
> This means that the kernel(s) are to be executed on HSA compatible
> runtimes such as AMD’s ROCm.
>
>
>
> > ..."enable_sgpr_dispatch_ptr = 1". Can I do something to turn that off
> in the...