Displaying 8 results from an estimated 8 matches for "amdgpuisd".
2016 Mar 25
2
RFC: atomic operations on SI+
...und a way to say 'output = the
first subreg for input or output = input' in pattern constraints.
2.) I think these will need SLC bit set to work correctly on HSA
targets. I'm not sure what the best way is to do this. I considered:
* adding it as an operand to the newly introduced node
(AMDGPUISD::CMP_SWAP), and setting it to 0/1 in Lowering pass. Can this
be done without changing order of the inputs? slc is always the last
but the count is variable
* introducing HSA variants of the instructions with SLC bit set
* setting the bit in DAG combine (is there a way to know if I'm
combining a...
2016 Mar 28
0
RFC: atomic operations on SI+
...the
> first subreg for input or output = input' in pattern constraints.
>
> 2.) I think these will need SLC bit set to work correctly on HSA
> targets. I'm not sure what the best way is to do this. I considered:
> * adding it as an operand to the newly introduced node
> (AMDGPUISD::CMP_SWAP), and setting it to 0/1 in Lowering pass. Can this
> be done without changing order of the inputs? slc is always the last
> but the count is variable
> * introducing HSA variants of the instructions with SLC bit set
> * setting the bit in DAG combine (is there a way to know if...
2014 Oct 03
2
[LLVMdev] Weird problems with cos (was Re: [PATCH v3 2/3] R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO)
...rc1) | (~src0 & src2)
> diff --git a/lib/Target/R600/AMDGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td
> index 3d70791..1600c4a 100644
> --- a/lib/Target/R600/AMDGPUInstrInfo.td
> +++ b/lib/Target/R600/AMDGPUInstrInfo.td
> @@ -91,6 +91,12 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
> [SDNPCommutative, SDNPAssociative]
> >;
>
> +// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
> +def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
> +
> +// out = (src1 > src0) ? 1 : 0
> +def AMDGPUborrow : S...
2020 Jul 16
2
Selection DAG chain question
...d support natively.
>
>
> You can’t add arbitrary chains or glue to the regular nodes, but you can
> define a custom node you select the same way with your chain/glue. You
> don’t need to preprocess the IR and can do in the custom lowering. This is
> what AMDGPU does for FDIV (see AMDGPUISD::FMA_W_CHAIN). GlobalISel avoids
> these complications by not having nodes or chains, and just instructions
> with side effects, so in that sense this is a solved problem.
>
> -Matt
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org...
2020 Jul 16
2
Selection DAG chain question
> No, non-sideeffecting operations can be legalized as compiler-rt calls
Right, but not as "regular" nodes with side-effects? I guess you could
search and analyze the DAG manually but that seems hacky. Maybe something
that one day LLVM could support natively.
On Thu, Jul 16, 2020 at 11:55 AM Matt Arsenault <arsenm2 at gmail.com> wrote:
>
>
> On Jul 16, 2020, at
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
....getOperand(1));
> + case AMDGPUIntrinsic::AMDIL_fabs:
> + return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
> + case AMDGPUIntrinsic::AMDGPU_lrp:
> + return LowerIntrinsicLRP(Op, DAG);
> + case AMDGPUIntrinsic::AMDIL_fraction:
> + return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
> + case AMDGPUIntrinsic::AMDIL_mad:
> + return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
> + Op.getOperand(2), Op.getOperand(3));
> + case AMDGPUIntrinsic::AMDIL_max:
> + return DAG.getNode(AM...
2020 Jul 17
2
Selection DAG chain question
...d support natively.
>
>
> You can’t add arbitrary chains or glue to the regular nodes, but you can
> define a custom node you select the same way with your chain/glue. You
> don’t need to preprocess the IR and can do in the custom lowering. This is
> what AMDGPU does for FDIV (see AMDGPUISD::FMA_W_CHAIN). GlobalISel avoids
> these complications by not having nodes or chains, and just instructions
> with side effects, so in that sense this is a solved problem.
>
> -Matt
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev...
2020 Jul 20
2
Selection DAG chain question
...t;>> You can’t add arbitrary chains or glue to the regular nodes, but you can
>>> define a custom node you select the same way with your chain/glue. You
>>> don’t need to preprocess the IR and can do in the custom lowering. This is
>>> what AMDGPU does for FDIV (see AMDGPUISD::FMA_W_CHAIN). GlobalISel avoids
>>> these complications by not having nodes or chains, and just instructions
>>> with side effects, so in that sense this is a solved problem.
>>>
>>> -Matt
>>>
>>> _______________________________________________...