search for: amd_iommu_ioapic_update_ire

Displaying 4 results from an estimated 4 matches for "amd_iommu_ioapic_update_ire".

2012 Oct 18
3
[PATCH 1/1] keep iommu disabled until iommu_setup is called
...there is no iommu available xen crashes. This can happen for example when panic(...) is called that got introduced with patch "x86-64: detect processors subject to AMD erratum #121 and refuse to boot." since xen 4.1.3 and results in the following stacktrace: find_iommu_for_device amd_iommu_ioapic_update_ire timer_interrupt enable_8259_A_irq do_IRQ printk_start_of_line acpi_os_printf io_apic_write __ioapic_write_entry ioapic_write_entry __clear_IO_APIC_pin clear_IO_APIC disable_IO_APIC __stop_this_cpu smp_send_stop machine_restart panic tasklet_schedule_o...
2012 Oct 18
0
[PATCH 0/1] fix xen-crash at panic()-call during boot
...t on a AMD machine. This happens since patch "x86-64: detect processors subject to AMD erratum #121 and refuse to boot." Instead of the actual panic-message from the patch the following stacktrace appears (i typed it down from screen, so it might contain typos) find_iommu_for_device amd_iommu_ioapic_update_ire timer_interrupt enable_8259_A_irq do_IRQ printk_start_of_line acpi_os_printf io_apic_write __ioapic_write_entry ioapic_write_entry __clear_IO_APIC_pin clear_IO_APIC disable_IO_APIC __stop_this_cpu smp_send_stop machine_restart panic tasklet_schedule_on_cpu display_cacheinfo init_amd generic_identif...
2013 Oct 06
17
AMD IOMMU disabled - No Perdev Intremap
Hi! From other people posting to this list, I know that there has been a bug related to the issue described in Xen Security Advisory 36 that disables iommu for some AMD users like me. However, even when passing "iommu=no-amd-iommu-perdev-intremap" it still disables i/o virtualisatoin. Related Xen dmesg output: (XEN) IVHD Error: Invalid IO-APIC 0 (XEN) AMD-Vi: Error initialization
2011 Nov 18
5
[PATCH 0 of 4] amd iommu: IOMMUv2 support
This patch set adds basic supports for amd next generation iommu (IOMMUv2) hardware. IOMMUv2 supports various new features advertised by iommu extended feature register. It introduces guest level IO translation and supports state-of-the-art ATS/ATC devices with demand paging capability. Please refer to AMD IOMMU Architectural Specification [1] for more details. Thanks, Wei [1]