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...other adding hardware to perform dynamic rescheduling and register renaming, which effectively replace these stack accesses with registers or access to fast cache. But, with upcoming architectures - particularly ones with a very large number of cores (e.g. something along the lines of Larrabee, or Ambric, and a plethora of others) - such hardware is too costly. As a result, needless stack activity consumes available memory bandwidth, which absolutely hammers instruction-level parallelism. I certainly agree that a fast default register allocator is the best strategy for LLVM, considering its main u...