search for: alue

Displaying 20 results from an estimated 217 matches for "alue".

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2012 Jun 22
4
Search list of elements for a specific pattern
Hi, I have a list of mutations, called "mutList", of the form: > head(mutList) Alu 1 AluJ 2 AluJ/F(R)AM 3 AluJ/FLAM 4 AluJ/FRAM 5 AluJ/monomer 6 AluJb It contains about 500 elements and not all of them contain the sequence "Alu". I tried using this code: Alu<-mutList[which(grep("Alu",mutList)==1)] But that simply returned
2008 Oct 21
1
behavior of ALU Scheduler
Hello, I have one question about the ALU scheduler. If for example I have one UNIFY volume which is using ALU scheduler with the following config: volume unify type cluster/unify option namespace afr-ns option scheduler rr option scheduler alu # use the ALU scheduler option alu.limits.min-free-disk 3% # Don't create files one a volume with less than 5% free diskspace
2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set
2011 May 14
0
Data is Copying when a new brick is added.
== Data Copying when a new brick is added. == Hi. I'm a first time glusterfs user, and I'm trying to simulate what will happen when I need to add more bricks for storage capacity. My config files are below but I'll try and explain what is going on. I have 2 machines with 2 hard drives in each. I created a replicated storage system where machine a replicates to machine b.
2015 Nov 12
2
Help making 'narrow instruct microcode' Backend
I've been experimenting with llvm/clang as a user for a while now, but now I'm interested in writing my own backend. I'm also developing the target architecture (maybe to go in an fpga eventually) and I'm intentionally making it extremely simple. I think of it as a narrow microcode, because (for example) performing an add requires a sequence of instructions like: set aluin1 = r1
2008 Dec 14
1
Is that iozone result normal?
5-nodes server and 1 node client are connected by gigabits Ethernet. #] iozone -r 32k -r 512k -s 8G KB reclen write rewrite read reread read write read rewrite read fwrite frewrite fread freread 8388608 32 10559 9792 62435 62260 8388608 512 63012 63409 63409 63138 It seems 32k write/rewrite performance are very
2009 Jun 11
2
Issue with files on glusterfs becoming unreadable.
elbert at host1:~$ dpkg -l|grep glusterfs ii glusterfs-client 1.3.8-0pre2 GlusterFS fuse client ii glusterfs-server 1.3.8-0pre2 GlusterFS fuse server ii libglusterfs0 1.3.8-0pre2 GlusterFS libraries and translator modules I have 2 hosts set up to use AFR with
2016 Mar 25
3
NEON FP flags
On 25 March 2016 at 04:11, Hal Finkel <hfinkel at anl.gov> wrote: > As I understand it, the fundamental property being addresses here is: Are the semantics of scalar FP math the same as vector FP math? TTI seems like a good place to expose that information. If the semantics are indeed different, then the vectorizer would require fast-math flags in order to vectorize FP operations
2005 Jun 30
1
Re: Hot swap CPU -- "build" is not a good CPU benchmark
From: Peter Arremann <loony at loonybin.org> > Compiles aren't a great benchmark for a box since its 100% cpu and > neglects memory or disk performance but I had the numbers handy > for that :-) BTW, it is 100% ALU and a major strain on the ALU LOAD. In other words, it's not a good benchmark for even CPU. That's why the 3-issue ALU in the Nx586 on-ward blows the
2009 Oct 22
1
[PATCH] nv04-nv40/exa: Reorder the commands in PrepareCopy to match the blob.
This fixes a somewhat indeterministic corruption problem on nv17 when there is stuff going on the other fifos (e.g. gallium but I've also reproduced it with an app just SIFM-ing memory around): in some cases it made the blits the X server had scheduled use the wrong pitch. Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- src/nv04_exa.c | 22 ++++++++++++---------- 1
2010 Apr 16
1
data frame manipulation
Dear group, Here is my data.frame : df <- structure(list(DESCRIPTION = c("PRM HGH GD ALU", "PRM HGH GD ALU", "PRIMARY NICKEL", "PRIMARY NICKEL", "PRIMARY NICKEL", "PRIMARY NICKEL", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ",
2019 Jun 07
2
[llvm-mca] What's the difference between Rthroughput and "total cycles" in llvm-mca
Hi Andrea, So does this definition make sense for basic blocks with more than one instructions? E.g. how should one interpret a basic block with RThroughput of 2.3? On Fri, Jun 7, 2019 at 7:39 AM Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > Hi Tom, > > Field 'Total Cycles' from the summary view simply reports the elapsed > number of cycles for the entire
2011 Apr 08
3
[LLVMdev] Macro-op fusion experiment
On Apr 8, 2011, at 9:56 AM, NAKAMURA Takumi wrote: >>> 8B C3 mov eax, ebx >>> 03 C1 add eax, ecx >>> becomes >>> 8B C3 03 C1 add eax, ebx, ecx > > In my understanding, twoaddr pass tends to emit such a sequence. Yes, it always does, and the coalescer tries very hard to eliminate the copy. > Though I
2013 Feb 11
2
[LLVMdev] DFAPacketizer
Jonas, At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing. -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST:
2016 Mar 29
1
NEON FP flags
...te that floating-point operations are **not** generated by GCC's auto-vectorization pass **unless** -funsafe-math-optimizations is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision. That is to say, GCC will only auto-vectorize floationg-point arithmetic if both -mfpu=neon AND -funsafe-math-optimizations are given. -mfpu=neon by itself does not imply that it is OK for GCC to generat...
2009 Oct 31
0
[PATCH] nv/exa: fix 15/16 bits solid fill
From: Marcin Slusarz <marcin.slusarz at gmail.com> after this change nouveau passes all fill and blend tests of rendercheck (before: fill - 108/120, blend - 3323868/3569150) tested on NV34 Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- src/nv04_exa.c | 19 +++++++++---------- src/nv_accel_common.c | 5 ++++- 2 files changed, 13 insertions(+), 11
2017 Sep 21
0
[iovisor-dev] [PATCH RFC 0/4] Initial 32-bit eBPF encoding support
On Wed, Sep 20, 2017 at 12:20:40AM +0100, Jiong Wang via iovisor-dev wrote: > On 18/09/2017 22:29, Daniel Borkmann wrote: > > On 09/18/2017 10:47 PM, Jiong Wang wrote: > > > Hi, > > > > > >    Currently, LLVM eBPF backend always generate code in 64-bit mode, > > > this may > > > cause troubles when JITing to 32-bit targets. > > >
2015 May 19
2
[PATCH 1/2] Check before trying a solid fill
Pre-nv50 has all sorts of funny requirements for non-copy alu operations, and will bail out of solid fills left and right. Account for that case and fall back to the memset. Reported-by: Andrew Randrianasulu <randrianasulu at gmail.com> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/drmmode_display.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)
2015 Oct 19
2
Instructions with no operand
Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,