Displaying 4 results from an estimated 4 matches for "alu32_rr".
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...ommit last week regarding
TRI::getCommonSuperRegClass(). Can that have a role to play here?
FWIW, the relevant patterns for COMBINE_rr are shown below.
------------------------------------------------------------------
// Combine.
let isPredicable = 1, neverHasSideEffects = 1 in
def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = combine($src1, $src2)",
[]>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),...
2013 Mar 23
0
[LLVMdev] Simpler types in TableGen isel patterns
On Thu, Mar 21, 2013 at 2:26 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
> Currently, instruction selection patterns are defined like this:
>
> def : Pat<(and (not GR32:$src1), GR32:$src2),
> (ANDN32rr GR32:$src1, GR32:$src2)>;
> def : Pat<(and (not GR64:$src1), GR64:$src2),
> (ANDN64rr GR64:$src1, GR64:$src2)>;
>
>
2013 Mar 21
9
[LLVMdev] Simpler types in TableGen isel patterns
Currently, instruction selection patterns are defined like this:
def : Pat<(and (not GR32:$src1), GR32:$src2),
(ANDN32rr GR32:$src1, GR32:$src2)>;
def : Pat<(and (not GR64:$src1), GR64:$src2),
(ANDN64rr GR64:$src1, GR64:$src2)>;
TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the register
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...+ Requires<[HasV4T]>;
>> +
>> // Hexagon V4 Architecture spec defines 8 instruction classes:
>> // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
>> // compiler)
>> @@ -250,23 +255,151 @@ def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
>> []>,
>> Requires<[HasV4T]>;
>>
>> +// Generate frame index addresses.
>> +let neverHasSideEffects = 1, isReMaterializable = 1 in
>> +def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
>> +...