Displaying 7 results from an estimated 7 matches for "alu2".
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2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...#39;MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST: InstrItinClass;
def ALU1: ProcResource<1>;
def ALU2: ProcResource<1>;
def WriteALU1: SchedWriteRes<[ALU1]> { let Latency = 1; }
def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; }
def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]>
From this example, we can access the latency information of MI with
'getWriteLatency...
2013 Feb 11
2
[LLVMdev] DFAPacketizer
...ems writing the ProcessorItineraries list. As
instructions on my VLIW target have varying size I want to model both
cpu units and bundle bits as FUs. The following does not work, to my
surprise:
InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
InstrStage<1, [ALU1, ALU2]>]>
I want to express that there are two ALU's, and four bundle slots, and
in this case while allocating this type of instructions several times, I
would like to be allowed only two such instructions per cycle.
ResourceTracker->reserveResources();
ResourceTracker->reserveResour...
2013 Feb 12
2
[LLVMdev] DFAPacketizer
...es list. As
> instructions on my VLIW target have varying size I want to model both
> cpu units and bundle bits as FUs. The following does not work, to my
> surprise:
>
> InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
>
> InstrStage<1, [ALU1, ALU2]>]>
>
> I want to express that there are two ALU's, and four bundle slots, and
> in this case while allocating this type of instructions several times,
> I would like to be allowed only two such instructions per cycle.
>
> ResourceTracker->reserveResources();
>
&...
2013 Feb 12
0
[LLVMdev] DFAPacketizer
...neraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise:
InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
InstrStage<1, [ALU1, ALU2]>]>
I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle.
ResourceTracker->reserveResources();
ResourceTracker->reserveResources...
2013 Feb 18
0
[LLVMdev] DFAPacketizer
...neraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise:
InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
InstrStage<1, [ALU1, ALU2]>]>
I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle.
ResourceTracker->reserveResources();
ResourceTracker->reserveResources...
2014 Jan 28
3
[LLVMdev] New machine model questions
From: Andrew Trick [mailto:atrick at apple.com]
Sent: 24 January 2014 21:52
To: Daniel Sanders
Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu)
Subject: Re: New machine model questions
On Jan 24, 2014, at 2:21 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at imgtec.com>> wrote:
Hi Andrew,
I seem to be making good progress on the P5600 scheduler
2013 Feb 11
0
[LLVMdev] DFAPacketizer
...neraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise:
InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
InstrStage<1, [ALU1, ALU2]>]>
I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle.
ResourceTracker->reserveResources();
ResourceTracker->reserveResources...