search for: alu1

...39;MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST: InstrItinClass; def ALU1: ProcResource<1>; def ALU2: ProcResource<1>; def WriteALU1: SchedWriteRes<[ALU1]> { let Latency = 1; } def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; } def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]> From this example, we can access the latency information...

...problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserve...

...peline and a load/store pipeline./ > > /Look into ARM itineraries, they contain a decent amount of such > examples./ > > // > > [Head feb 2013:] > > InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, > > InstrStage<1, [SW_ALU0, SW_ALU1]>], > > [1]>, > > ------------------------------------------------------------------------ > > *From:*Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] > *Sent:* Monday, February 11, 2013 7:19 PM > *To:* Jonas Paulsson; llvmdev at cs.u...

...a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples. [Head feb 2013:] InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, InstrStage<1, [SW_ALU0, SW_ALU1]>], [1]>, ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Monday, February 11, 2013 7:19 PM To: Jonas Paulsson; llvmdev at cs.uiuc.edu Subject: RE: DFAPacketizer Jonas, At this point, the DFA packet...

...a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples. [Head feb 2013:] InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, InstrStage<1, [SW_ALU0, SW_ALU1]>], [1]>, ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Monday, February 11, 2013 7:19 PM To: Jonas Paulsson; llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: RE: DFAPacketizer J...

...sorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveRes...

...no other instruction may be issued to that unit, then I need to do this: [InstrStage<2, [NonPipelinedUnit]> If I have an instruction that splits into two dependent microops, that use the same type of functional unit, but at different times, then I need to do this: [InstrStage<1, [ALU0, ALU1], 1> InstrStage<1, [ALU0, ALU1]> -Andy >From TargetScheduled.td: //===----------------------------------------------------------------------===// // Instruction stage - These values represent a non-pipelined step in // the execution of an instruction. Cycles represents the number of...