Displaying 3 results from an estimated 3 matches for "altvsxfmarel".
2017 May 30
2
Pseudo-instruction that overwrites its input register
...frc:$XB),
"xsmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
AltVSXFMARel;
If I'm reading this right, this matches an instruction that updates $XT
by taking the current $XT, and two extra args in $XA and $XB. However, my
situation would be something akin to
(set f64:$XC, (fma f64:$XA, f64:$XB, f64:$XTi))
with the extra constraint that $XTi is overwritten in the...
2017 May 28
2
Pseudo-instruction that overwrites its input register
On Sun, 28 May 2017, David Chisnall wrote:
>> let Constraints = "@earlyclobber $reg" in
>> def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>> (ins PTRREGS:$ptrreg),
>> "ldw\t$reg, $ptrreg",
>> [(set i16:$reg, (load i16:$ptrreg))]>,
>>
2017 May 30
1
Pseudo-instruction that overwrites its input register
..."xsmaddadp $XT, $XA, $XB", IIC_VecFP,
> [(set f64:$XT, (fma f64:$XA, f64:$XB,
> f64:$XTi))]>,
> RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
> AltVSXFMARel;
>
> If I'm reading this right, this matches an instruction that updates $XT by
> taking the current $XT, and two extra args in $XA and $XB. However, my
> situation would be something akin to
>
> (set f64:$XC, (fma f64:$XA, f64:$XB, f64:$XTi))
>
> with the extra constrai...