Displaying 2 results from an estimated 2 matches for "altorderselect".
2011 Jun 15
0
[LLVMdev] Custom allocation orders
...lternative syntax for the same thing:
def GR8 : RegisterClass<"X86", [i8], 8,
[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
let AltOrders = [(sub GR8, AH, BH, CH, DH)];
let AltOrderSelect = [{
const TargetMachine &TM = MF.getTarget();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
return Subtarget.is64Bit();
}];
}
The AltOrders field is a list of dags, each describing an alternative allocation order. The AltOrderSelect field is a snippe...
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
...egisters that is not included in the existing set of
RegisterClass definitions. More concretely, there is a RegisterClass in
ARMRegisterInfo.td defined as
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
However, I'd like the instruction NOT to use the LR. I don't see an existing
RegisterClass defined with R0_R12; something like:
def newGPR : RegisterClass<"ARM", [i32], 3...