Displaying 3 results from an estimated 3 matches for "altorders".
2011 Jun 15
0
[LLVMdev] Custom allocation orders
...t infer derived register classes.
Here is an alternative syntax for the same thing:
def GR8 : RegisterClass<"X86", [i8], 8,
[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
let AltOrders = [(sub GR8, AH, BH, CH, DH)];
let AltOrderSelect = [{
const TargetMachine &TM = MF.getTarget();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
return Subtarget.is64Bit();
}];
}
The AltOrders field is a list of dags, each describing an alternative al...
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
...articular pseudo-instruction to
choose from a set of registers that is not included in the existing set of
RegisterClass definitions. More concretely, there is a RegisterClass in
ARMRegisterInfo.td defined as
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
However, I'd like the instruction NOT to use the LR. I don't see an existing
RegisterClass defined with R0_R12; something like:...
2018 Jan 17
1
Opcodes with 32-bit pair vs 64-bit register
Mark, did you get anywhere with this? We have a similar issue, where a family of otherwise-identical instructions operates on different register classes depending on a non-static property -- functional unit selection in our case.
I started to head down the path of using multidefs but quickly abandoned that. I had envisioned a MachineOperand that would hold the functional unit assignment, and