Displaying 3 results from an estimated 3 matches for "altivee".
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altivec
2016 Feb 29
2
[GSoC 2016] Code Generation Improvements task
...s.
3. lib/Target/AArch64/AArch64PromoteConstant.cpp
This pass tries to simplify aggregate data like struct of const with
special SIMD instructions available on the system. For example on ARM its
NEON similarly other architectures have SIMD support specifically MIPS, IBM
System Z, Power PC with MMX/AltiVee and x86 with Intel’s AVX.
Apart from these , The proposal can include task for merging the delay slot
filling logic ( from Sparc and Mips ) into single target independent pass.
These is just a primary investigation. I am not expert with all
architectures supposed by LLVM but MIPS, x86 and to some...
2016 Mar 01
2
[GSoC 2016] Code Generation Improvements task
...rch64/AArch64PromoteConstant.cpp
> This pass tries to simplify aggregate data like struct of const with special
> SIMD instructions available on the system. For example on ARM its NEON
> similarly other architectures have SIMD support specifically MIPS, IBM
> System Z, Power PC with MMX/AltiVee and x86 with Intel’s AVX.
Possibly. It seems to rely pretty strongly on ARM's "load more than
you can actually use" instructions: vldN instructions can load up to 4
128-bit vectors, but they can still only be used as 128-bit vectors.
If other targets possess similar, then they could...
2016 Mar 01
0
[GSoC 2016] Code Generation Improvements task
...ant.cpp
> > This pass tries to simplify aggregate data like struct of const with
> special
> > SIMD instructions available on the system. For example on ARM its NEON
> > similarly other architectures have SIMD support specifically MIPS, IBM
> > System Z, Power PC with MMX/AltiVee and x86 with Intel’s AVX.
>
> Possibly. It seems to rely pretty strongly on ARM's "load more than
> you can actually use" instructions: vldN instructions can load up to 4
> 128-bit vectors, but they can still only be used as 128-bit vectors.
> If other targets possess s...