search for: alphaisellowering

...bb1 ] br label %return This compiles correctly when I use the X86 or PPC backend, but results in the following error with Alpha backend: LLVM ERROR: Cannot select: 0x95a0490: i64 = BlockAddress<@main, %bb1> [ID=3] I also found the following line commented out in the file lib/Target/Alpha/AlphaISelLowering.cpp: // setOperationAction(ISD::BRIND, MVT::Other, Expand); My guess is that indirectbr is not implemented for Alpha. If that's the case, where do I need to make changes to implement this instruction? Thank you, Giang -------------- next part -------------- An HTML attachment was...

...ers like %d0 and %d1 > and result comes on %d0? Do I need to allocate virtual regs for them > and pre-assign physical regs somehow? > > Or my be I have to define a new calling convention that would enforce > it? The Alpha backend does this for division and remainder of integers. See AlphaISelLowering.cpp:501 for the lowering to a custom call node, then AlphaISelDAGToDAG.cpp:215 for the enforcing of the register constraints (copy into/out of physical registers), then AlphaInsrInfo.td:476 (JSRs) for the call instruction with special register DEF/USE sets to match the calling convention of the lib...

Hi, >> My target supports only f64 at the moment. >> Question: How can I tell LLVM that float is the same as double on my >> target? May be by assigning the same register class to both MVT::f32 ?> and MVT::f64? >Just don't assign a register class for the f32 type. This is what the >X86 backend does when it is in "floating point stack mode". This will

Hi all, There's been a recent bootstrap failure that might be covered up because of another failure. I just wanted to point this out so that people can take a look: -bw Here's the failure from our buildbot: Assertion failed: (DestReg == VirtReg && "Unknown load situation!"), function RewriteMBB, file /Volumes/Sandbox/Buildbot/llvm/build.llvm-