search for: allreg

...g on an LLVM backend for a new target architecture. This architecture has two single-ported register files. Each instruction can only read one operand from each register file, but can write to either. I tried implementing it naïvely in TableGen with two definitions per instruction, so I had: def AllRegs : RegisterClass< ... (add interleave (XRegs, YRegs))>; and in the InstrInfo.td: def Instr_xy: Instruction(outs AllRegs:$dst), (ins XRegs:$src1, YRegs:$src2), "...", [(set AllRegs:$dst, (OpNode XRegs:$src1, YRegs:$src2))] def Instr_yx: Instruction(outs AllRegs:$dst), (ins YRegs:$...

...", [i16], 8, (add AD, IX, IY, SU, SS, PC, AW, AV, A0)>; def GR32 : RegisterClass<"MC6809", [i32], 8, (add AQ)>; def IX16 : RegisterClass<"MC6809", [i16], 8, (add IX, IY, SU, SS)>; def WREG : RegisterClass<"MC6809", [i16], 8, (add AW)>; def ALLREG : RegisterClass<"MC6809", [i8, i16], 8, (add AD, IX, IY, SU, SS, PC, AW, AV, AA, AB, CC, DP, A0, AE, AF)>; //===----------------------------------------------------------------------===// (The extra registers are for the Hitachi HD6309 extended version) TableGen doesn't like t...

...etflag) - Complexity = 3 // Dst: (RETL) /*4322*/ /*Scope*/ 11, /*->4334*/ /*4323*/ OPC_RecordNode, // #0 = $a /*4324*/ OPC_CheckType, MVT::i32, /*4326*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::MVrr), 0, 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Src: AllRegs:i32:$a - Complexity = 3 // Dst: (MVrr:i32 AllRegs:i32:$a) /*4334*/ /*Scope*/ 14, /*->4349*/ /*4335*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD), /*4338*/ OPC_RecordChild0, // #0 = $a /*4339*/ OPC_RecordChild1, // #1 = $b /*4340*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::ADDrrr)...

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

https://bugs.freedesktop.org/show_bug.cgi?id=93004 Bug ID: 93004 Summary: Guild Wars 2 crash on nouveau DX11 cards Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.